xllp_usbohci.h

Intel PXA270底层设备驱动代码

#ifndef __XLLP_USBHOST_H__
#define __XLLP_USBHOST_H__

/******************************************************************************
**
**  COPYRIGHT (C) 2002 Intel Corporation.
**
**  This software as well as the software described in it is furnished under
**  license and may only be used or copied in accordance with the terms of the
**  license. The information in this file is furnished for informational use
**  only, is subject to change without notice, and should not be construed as
**  a commitment by Intel Corporation. Intel Corporation assumes no
**  responsibility or liability for any errors or inaccuracies that may appear
**  in this document or any software that may be provided in association with
**  this document. 
**  Except as permitted by such license, no part of this document may be 
**  reproduced, stored in a retrieval system, or transmitted in any form or by
**  any means without the express written consent of Intel Corporation. 
**
**  FILENAME:   xllp_usbohci.h
**
**  PURPOSE:    contains all PXA27x specific XLLP USB OHCI typedefs and bit definitions..
**
******************************************************************************/

#ifdef __cplusplus
extern "C" {
#endif

#include "xllp_defs.h"
#include "xllp_gpio.h"
#include "xllp_bcr.h"
#include "xllp_clkmgr.h"
#include "xllp_ost.h"
#include "xllp_usbohci_platform.h"

//
// Current to PXA27x Processor Family Developer's Manual
//

// XLLP compliant declaration

//
// USB HOST OHCI (USBOHCI) Register Bank
//
typedef struct _XLLP_USBOHCI_S

{
    XLLP_VUINT32_T    UHCREV;		// HCI Spec Revision
    XLLP_VUINT32_T    UHCHCON;		// Control register
    XLLP_VUINT32_T    UHCCOMS;		// Command Status
    XLLP_VUINT32_T    UHCINTS;		// Interrupt Status
    XLLP_VUINT32_T    UHCINTE;		// Interrupt Enable Control register
    XLLP_VUINT32_T    UHCINTD;		// Interrupt Disable Control register
    XLLP_VUINT32_T    UHCHCCA;		// Host controller Communication Area
    XLLP_VUINT32_T    UHCPCED;		// Period Current Endpoint Descriptor
    XLLP_VUINT32_T    UHCCHED;		// Control Head Endpoint Descriptor register
    XLLP_VUINT32_T    UHCCCED;		// Control Current Endpoint Descriptor register
    XLLP_VUINT32_T    UHCBHED;		// Bulk Head Endpoint Descriptor register
    XLLP_VUINT32_T    UHCBCED;		// Bulk Current Endpoint Descriptor register
    XLLP_VUINT32_T    UHCDHEAD;		// Done head register
    XLLP_VUINT32_T    UHCFMI;		// Frame Interval register
    XLLP_VUINT32_T    UHCFMR;		// Frame Remaining register
    XLLP_VUINT32_T    UHCFMN;		// Frame Number register
    XLLP_VUINT32_T    UHCPERS;		// Periodic Start register
    XLLP_VUINT32_T    UHCLST;		// Low Speed Threshold register
    XLLP_VUINT32_T    UHCRHDA;		// Root Hub Descriptor A register
    XLLP_VUINT32_T    UHCRHDB;		// Root Hub Descriptor B register
    XLLP_VUINT32_T    UHCRHS;		// Root Hub Status register
    XLLP_VUINT32_T    UHCRHPS1;		// Root Hub Port 1 Status register
    XLLP_VUINT32_T    UHCRHPS2;		// Root Hub Port 2 Status register
    XLLP_VUINT32_T    UHCRHPS3;		// Root Hub Port 3 Status register
    XLLP_VUINT32_T    UHCSTAT;		// USB Host Status
    XLLP_VUINT32_T    UHCHR;		// USB Host Reset
    XLLP_VUINT32_T    UHCHIE;		// USB Host Interrupt Enable
    XLLP_VUINT32_T    UHCHIT;		// USB Host Interrupt Test

} XLLP_USBOHCI_T, *P_XLLP_USBOHCI_T;


// fields and bits for UHCREV:		HCI Spec Revision
#define XLLP_USBOHCI_UHCREV_OHCISPEC1_0_A		0x10

// fields and bits for UHCHCON:	 UHC Host Control register
// for the CBSR field
#define XLLP_USBOHCI_UHCHCON_CBSR_MASK			( 0x3u << 0 )
#define XLLP_USBOHCI_UHCHCON_CBSR_1_1			( 0x0u << 0 )
#define XLLP_USBOHCI_UHCHCON_CBSR_2_1			( 0x1u << 0 )
#define XLLP_USBOHCI_UHCHCON_CBSR_3_1			( 0x2u << 0 )
#define XLLP_USBOHCI_UHCHCON_CBSR_4_1			( 0x3u << 0 )

#define	XLLP_USBOHCI_UHCHCON_PLE			( 1u   << 2 )
#define	XLLP_USBOHCI_UHCHCON_IE				( 1u   << 3 )
#define	XLLP_USBOHCI_UHCHCON_CLE			( 1u   << 4 )
#define	XLLP_USBOHCI_UHCHCON_BLE			( 1u   << 5 )

// for the HCFS field
#define XLLP_USBOHCI_UHCHCON_HCFS_MASK		    ( 0x3u << 6 )
#define XLLP_USBOHCI_UHCHCON_HCFS_USBRESET		( 0u << 6 )
#define XLLP_USBOHCI_UHCHCON_HCFS_USBRESUME		( 1u << 6 )
#define XLLP_USBOHCI_UHCHCON_HCFS_USBOPERATIONAL    ( 2u << 6 )
#define XLLP_USBOHCI_UHCHCON_HCFS_USBSUSPEND		( 3u << 6 )

#define	XLLP_USBOHCI_UHCHCON_IR				( 1u  << 8 )
#define	XLLP_USBOHCI_UHCHCON_RWC			( 1u  << 9 )
#define	XLLP_USBOHCI_UHCHCON_RWE			( 1u  << 10 )



// fields and bits for UHCCOMS:	UHC Command Status register
#define	XLLP_USBOHCI_UHCCOMS_HCR				( 1u   << 0 )
#define	XLLP_USBOHCI_UHCCOMS_CLF				( 1u   << 1 )
#define	XLLP_USBOHCI_UHCCOMS_BLF				( 1u   << 2 )
#define	XLLP_USBOHCI_UHCCOMS_OCR				( 1u   << 3 )

#define XLLP_USBOHCI_UHCCOMS_SOC_MASK			( 0x3u << 16 )



// fields and bits for UHCINTS:		Interrupt Status register
// fields and bits for UHCINTE:		Interrupt Enable Control register
// fields and bits for UHCINTD:		Interrupt Disable Control register
// All the UHCINTS bits are Write 1 to clear bits
//
#define	XLLP_USBOHCI_UHCINT_SO					( 1u   << 0 )
#define	XLLP_USBOHCI_UHCINT_WDH					( 1u   << 1 )
#define	XLLP_USBOHCI_UHCINT_SF					( 1u   << 2 )
#define	XLLP_USBOHCI_UHCINT_RD					( 1u   << 3 )
#define	XLLP_USBOHCI_UHCINT_UE					( 1u   << 4 )
#define	XLLP_USBOHCI_UHCINT_FNO					( 1u   << 5 )
#define	XLLP_USBOHCI_UHCINT_RHSC				( 1u   << 6 )
#define	XLLP_USBOHCI_UHCINT_OC					( 1u   << 30 )
#define	XLLP_USBOHCI_UHCINT_MIE					( 1u   << 31 )

#define P_XLLP_USBOHCI_UHCINTS( pUsbhHandle ) ((pUsbhHandle)->pUSBHRegs->UHCINTS)

// Mask for write 1 to clear bits in UHCINTS
#define XLLP_USBOHCI_UHCINTS_MASK  (0xFFFFFFFF)
//#define XLLP_USBOHCI_UHCINTS_MWRITE( pUsbhHandle, y )  (P_XLLP_USBOHCI_UHCINTS( pUsbhHandle ) = (((P_XLLP_USBOHCI_UHCINTS( pUsbhHandle )) & (~XLLP_USBOHCI_UHCINTS_MASK)) | y))
//Optimized:
//#define XLLP_USBOHCI_UHCINTS_MWRITE( pUsbhHandle, y )    ((P_XLLP_USBOHCI_UHCINTS( pUsbhHandle )) = (y))
#define XLLP_USBOHCI_UHCINTS_MWRITE( pUsbhHandle, y )    (((pUsbhHandle)->pUSBHRegs->UHCINTS) = (y))
//To invoke, call:
//XLLP_USBOHCI_UHCINTS_MWRITE( pUsbhHandle, y)  

// fields and bits for UHCHCCA:		UHC Host controller Communication Area
#define XLLP_USBOHCI_UHCHCCA_MASK				( 0xffffffu << 8 )

// fields and bits for UHCPCED:		UHC Period Current Endpoint Descriptor
#define XLLP_USBOHCI_UHCPCED_MASK				( 0xfffffffu << 4 )

// fields and bits for UHCCHED:		UHC Control Head Endpoint Descriptor register
#define XLLP_USBOHCI_UHCCHED_MASK				( 0xfffffffu << 4 )

// fields and bits for UHCCCED:		UHC Control Current Endpoint Descriptor register
#define XLLP_USBOHCI_UHCCCED_MASK				( 0xfffffffu << 4 )

// fields and bits for UHCBHED:		UHC Bulk Head Endpoint Descriptor register
#define XLLP_USBOHCI_UHCBHED_MASK				( 0xfffffffu << 4 )

// fields and bits for UHCBCED:		UHC Bulk Current Endpoint Descriptor register
#define XLLP_USBOHCI_UHCBCED_MASK				( 0xfffffffu << 4 )

// fields and bits for UHCDHEAD:	UHC Done Head register
#define XLLP_USBOHCI_UHCDHED_MASK				( 0xfffffffu << 4 )	// should be "DHTD" because its a transfer descriptor

// fields and bits for UHCFMI:		UHC Frame Interval register
#define XLLP_USBOHCI_UHCFMI_FI_MASK				( 0x3fffu << 0 )
#define XLLP_USBOHCI_UHCFMI_FSMPS_MASK			( 0x7fffu << 16 )
#define	XLLP_USBOHCI_UHCFMI_FIT					( 1u   << 31 )

// fields and bits for UHCFMR:		UHC Frame Remaining register
#define XLLP_USBOHCI_UHCFMR_FR_MASK				( 0x3fffu << 0 )
#define	XLLP_USBOHCI_UHCFMI_FRT					( 1u   << 31 )

// fields and bits for UHCFMN:		UHC Frame Number register
#define XLLP_USBOHCI_UHCFMN_FN_MASK				( 0xffffu << 0 )

// fields and bits for UHCPERS:		UHC Periodic Start register
#define XLLP_USBOHCI_UHCPERS_PS_MASK			( 0x3fffu << 0 )

// fields and bits for UHCLST:		UHC Low Speed Threshold register
#define XLLP_USBOHCI_UHCPLST_LST_MASK			( 0xfffu << 0 )

// fields and bits for UHCRHDA:		UHC Root Hub Descriptor A register
#define XLLP_USBOHCI_UHCRHDA_NDP_MASK			( 0xffu << 0 )

#define	XLLP_USBOHCI_UHCRHDA_PSM				( 1u   << 8 )
#define	XLLP_USBOHCI_UHCRHDA_NPS				( 1u   << 9 )
#define	XLLP_USBOHCI_UHCRHDA_DT					( 1u   << 10 )
#define	XLLP_USBOHCI_UHCRHDA_OCPM				( 1u   << 11 )
#define	XLLP_USBOHCI_UHCRHDA_NOCP				( 1u   << 12 )

#define XLLP_USBOHCI_UHCRHDA_POTPGT_MASK		( 0xffu << 24 )

// fields and bits for UHCRHDB:		UHC Root Hub Descriptor B register
#define XLLP_USBOHCI_UHCRHDB_DR_MASK			( 0xffffu << 0 )
#define XLLP_USBOHCI_UHCRHDB_DR_PORT_1_REMOVABLE  ( 0x1u << 1 )
#define XLLP_USBOHCI_UHCRHDB_DR_PORT_2_REMOVABLE  ( 0x1u << 2 )
#define XLLP_USBOHCI_UHCRHDB_DR_PORT_3_REMOVABLE  ( 0x1u << 3 )

#define XLLP_USBOHCI_UHCRHDB_PPCM_MASK			( 0xffffu << 16 )
#define XLLP_USBOHCI_UHCRHDB_PPCM_PORT_1		( 0x1u << 17 )
#define XLLP_USBOHCI_UHCRHDB_PPCM_PORT_2		( 0x1u << 18 )
#define XLLP_USBOHCI_UHCRHDB_PPCM_PORT_3		( 0x1u << 19 )

// fields and bits for UHCRHS:		UHC Root Hub Status register
#define	XLLP_USBOHCI_UHCRHS_LPS					( 1u   << 0 )		// meaning on read
#define	XLLP_USBOHCI_UHCRHS_CGP					( 1u   << 0 )		// Write 1 to clear

#define	XLLP_USBOHCI_UHCRHS_OCI					( 1u   << 1 )

#define	XLLP_USBOHCI_UHCRHS_DRWE				( 1u   << 15 )		// meaning on read
#define	XLLP_USBOHCI_UHCRHS_SRWE				( 1u   << 15 )		// Write 1 to set

#define	XLLP_USBOHCI_UHCRHS_LPSC				( 1u   << 16 )		// meaning on read
#define	XLLP_USBOHCI_UHCRHS_SGP					( 1u   << 16 )		// meaning on write 1 to set

#define	XLLP_USBOHCI_UHCRHS_OCIC				( 1u   << 17 )      // Read/Write 1 to clear
#define	XLLP_USBOHCI_UHCRHS_CRWE				( 1u   << 31 )

#define P_XLLP_USBOHCI_UHCRHS( pUsbhHandle ) ((pUsbhHandle)->pUSBHRegs->UHCRHS)

// Mask for write 1 to clear bits in UHCRHS
#define XLLP_USBOHCI_UHCRHS_MASK  (XLLP_USBOHCI_UHCRHS_CGP | XLLP_USBOHCI_UHCRHS_OCIC)
//For sticky bits:
#define XLLP_USBOHCI_UHCRHS_MWRITE( pUsbhHandle, y )  (P_XLLP_USBOHCI_UHCRHS( pUsbhHandle ) = (((P_XLLP_USBOHCI_UHCRHS( pUsbhHandle )) & (~XLLP_USBOHCI_UHCRHS_MASK)) | y))
//For non-sticky bits:
//To set bits, above macro is enough.
//XLLP_USBOHCI_UHCRHS_MWRITE( pUsbhHandle, y) 
//To clear bit, the bit needs to be added to the mask.
#define XLLP_USBOHCI_UHCRHS_MWRITE_CLEAR_NON_STICKY(pUsbhHandle, y)     ( (P_XLLP_USBOHCI_UHCRHS( pUsbhHandle )) = ( (P_XLLP_USBOHCI_UHCRHS( pUsbhHandle )) &  (~(XLLP_USBOHCI_UHCRHS_MASK | y))) )

//To clear sticky bits and to set non-sticky bits, call:
//XLLP_USBOHCI_UHCRHS_MWRITE( pUsbhHandle, y) 
//To clear non-sticky bits, call: 
//#define XLLP_USBOHCI_UHCRHS_MWRITE_CLEAR_NON_STICKY(pUsbhHandle, y)


// fields and bits for UHCRHPS1:	UHC Root Hub Port 1 Status register
// fields and bits for UHCRHPS2:	UHC Root Hub Port 2 Status register
// fields and bits for UHCRHPS3:	UHC Root Hub Port 3 Status register
#define	XLLP_USBOHCI_UHCRHPS_CCS				( 1u   << 0 )
#define	XLLP_USBOHCI_UHCRHPS_PES				( 1u   << 1 )
#define	XLLP_USBOHCI_UHCRHPS_PSS				( 1u   << 2 )