📄 xllp_arm_primitives.s
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;******************************************************************************
;
; COPYRIGHT (C) 2005 Intel Corporation.
;
; This software as well as the software described in it is furnished under
; license and may only be used or copied in accordance with the terms of the
; license. The information in this file is furnished for informational use
; only, is subject to change without notice, and should not be construed as
; a commitment by Intel Corporation. Intel Corporation assumes no
; responsibility or liability for any errors or inaccuracies that may appear
; in this document or any software that may be provided in association with
; this document.
;
; Except as permitted by such license, no part of this document may be
; reproduced, stored in a retrieval system, or transmitted in any form or by
; any means without the express written consent of Intel Corporation.
;
;******************************************************************************
; PURPOSE:
; Provide ARM CPU primitive functions (eg. register access) for C code use
AREA |.text|, CODE, READONLY, ALIGN=5 ; Align =5 required for "ALIGN 32" to work
;
; Functions made public by this file:
;
EXPORT Xllp_Get_ARM_CPSR
EXPORT Xllp_Set_ARM_CPSR
EXPORT Xllp_Get_ARM_SPSR
EXPORT Xllp_Set_ARM_SPSR
EXPORT Xllp_Get_ARM_SP
EXPORT Xllp_Set_ARM_SP
EXPORT Xllp_Get_ARM_CPAR
EXPORT Xllp_Set_ARM_CPAR
EXPORT XllpCpuIdle
EXPORT XllpCpuStandby
INCLUDE xllp_ARM_macros.inc ; for RETURN macro
;**************************************************************************************************
Xllp_Get_ARM_CPSR FUNCTION
mrs r0, cpsr
RETURN
ENDFUNC
Xllp_Set_ARM_CPSR FUNCTION
msr cpsr, r0
RETURN
ENDFUNC
Xllp_Get_ARM_SPSR FUNCTION
mrs r0, spsr
RETURN
ENDFUNC
Xllp_Set_ARM_SPSR FUNCTION
msr spsr, r0
RETURN
ENDFUNC
Xllp_Get_ARM_SP FUNCTION
mov r0, sp
RETURN
ENDFUNC
Xllp_Set_ARM_SP FUNCTION
mov sp, r0
RETURN
ENDFUNC
Xllp_Get_ARM_CPAR FUNCTION
mrc p15, 0, r0, c15, c1, 0
RETURN
ENDFUNC
Xllp_Set_ARM_CPAR FUNCTION
mcr p15, 0, r0, c15, c1, 0 ; store to CPAR
;CPWAIT $R0
mrc p15, 0, r0, c2, c0, 0 ; arbitrary read of CP15
mov r0, r0 ; wait for it (foward dependency)
sub pc, pc, #4 ; branch to next instruction
RETURN
ENDFUNC
XllpCpuIdle FUNCTION
mov r0, #1
mcr p14, 0, r0, c7, c0, 0 ; Enter Idle mode
RETURN
ENDFUNC
XllpCpuStandby FUNCTION
mov r0, #2
mcr p14, 0, r0, c7, c0, 0 ; Enter Standby mode
nop
nop
nop
nop
nop
nop
nop
RETURN
ENDFUNC
;------------------------------------------
END
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