📄 xllp_usbohci.c
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/******************************************************************************
**
** COPYRIGHT (C) 2002 Intel Corporation.
**
** This software as well as the software described in it is furnished under
** license and may only be used or copied in accordance with the terms of the
** license. The information in this file is furnished for informational use
** only, is subject to change without notice, and should not be construed as
** a commitment by Intel Corporation. Intel Corporation assumes no
** responsibility or liability for any errors or inaccuracies that may appear
** in this document or any software that may be provided in association with
** this document.
** Except as permitted by such license, no part of this document may be
** reproduced, stored in a retrieval system, or transmitted in any form or by
** any means without the express written consent of Intel Corporation.
**
** FILENAME: xllp_usbohci.c
**
** PURPOSE: XLLP USB Host APIs - chip specific
**
** Valid for : PXA27x
**
**
******************************************************************************/
#include "xllp_usbohci.h"
#include "xllp_usbohci_platform.h"
/*******************************************************************************
*
* FUNCTION: XllpUsbhReset
*
* DESCRIPTION: To Reset PXA27x USB Host
*
*
* INPUT PARAMETERS: P_XLLP_USBH_HANDLE_T pUsbhHandle
*
* RETURNS:
* Success: 0 (XLLP_USBH_SUCCESS)
* Failure:
*
* CALLS: XllpOstDelayMicroSeconds, XllpUsbhConfigPlatformSpecificUSBHReset
*
* CALLED BY: XllpUsbhPowerUp, HCD
*
* PROTOTYPE: XLLP_USBH_ERROR_T XllpUsbhReset(P_XLLP_USBH_HANDLE_T pUsbhHandle);
*
*
*******************************************************************************/
XLLP_USBH_ERROR_T XllpUsbhReset(P_XLLP_USBH_HANDLE_T pUsbhHandle)
{
// Do the reset for the Bulverde part.
// Two levels of reset need to be initiated:
// The OHCI core needs to be reset via the FHR bit,
// then the OHCI system bus interface needs to be reset via the FSBIR bit.
// Reset the OHC core and all OHC blocks driven by the 12 MHz clock, eg. write fifo, etc.
pUsbhHandle->pUSBHRegs->UHCHR |= XLLP_USBOHCI_UHCHR_FHR;
// Wait for ten micro seconds called for by spec.
XllpOstDelayMicroSeconds(pUsbhHandle->pOSTRegs, 10) ;
//Clear FHR bit to enable normal USBH functioning.
pUsbhHandle->pUSBHRegs->UHCHR &= ~XLLP_USBOHCI_UHCHR_FHR;
// reset the OHC system bus interface, eg. SBI, DMA blocks, fifos, etc.
pUsbhHandle->pUSBHRegs->UHCHR |= XLLP_USBOHCI_UHCHR_FSBIR;
// auto clears in 3 system bus clocks
while( pUsbhHandle->pUSBHRegs->UHCHR & XLLP_USBOHCI_UHCHR_FSBIR )
;
//Init Platform Specific Configuration for USBH Reset
//XllpUsbhInitPlatformSpecificConfig(pUsbhHandle);
//Call for Platform Specific Configuration for USBH Reset
XllpUsbhConfigPlatformSpecificUSBHReset(pUsbhHandle);
return (XLLP_USBH_SUCCESS);
}
/*******************************************************************************
*
* FUNCTION: XllpUsbhSelectPowerManagementMode
*
* DESCRIPTION: Used to select power managemen modes like No Power Switching (NPS),
* PowerSwitchingMode (PSM), Per Port power
*
*
* INPUT PARAMETERS: P_XLLP_USBH_HANDLE_T pUsbhHandle
*
*
* RETURNS:
* Success: 0 (XLLP_USBH_SUCCESS)
* Failure:
*
* CALLS: None.
*
* CALLED BY: XllpUsbhPowerUp
*
* PROTOTYPE: XLLP_USBH_ERROR_T XllpUsbhSelectPowerManagementMode (
* P_XLLP_USBH_HANDLE_T pUsbhHandle ,
* XLLP_UINT32_T PowerMode,
* XLLP_UINT32_T NumPorts,
* P_XLLP_UINT32_T pPortMode)
*
*
*******************************************************************************/
XLLP_USBH_ERROR_T XllpUsbhSelectPowerManagementMode (
P_XLLP_USBH_HANDLE_T pUsbhHandle ,
XLLP_UINT32_T PowerMode,
XLLP_UINT32_T NumPorts,
P_XLLP_UINT32_T pPortMode)
{
switch(PowerMode)
{
case XLLP_USBOHCI_PPM_NPS:
// set NO Power Switching mode
pUsbhHandle->pUSBHRegs->UHCRHDA |= XLLP_USBOHCI_UHCRHDA_NPS;
break;
case XLLP_USBOHCI_PPM_GLOBAL:
// make sure the NO Power Switching mode bit is OFF so Power Switching can occur
// make sure the PSM bit is CLEAR, which allows all ports to be controlled with
// the GLOBAL set and clear power commands
//pUsbhHandle->pUSBHRegs->UHCRHDA &= ~(XLLP_USBOHCI_UHCRHDA_NPS|XLLP_USBOHCI_UHCRHDA_PSM);
pUsbhHandle->pUSBHRegs->UHCRHDA &= ~(XLLP_USBOHCI_UHCRHDA_NPS);
pUsbhHandle->pUSBHRegs->UHCRHDA &= ~(XLLP_USBOHCI_UHCRHDA_PSM);
break;
case XLLP_USBOHCI_PPM_PERPORT:
// make sure the NO Power Switching mode bit is OFF so Power Switching can occur
// make sure the PSM bit is SET, which allows all ports to be controlled with
// the PER PORT set and clear power commands
pUsbhHandle->pUSBHRegs->UHCRHDA &= ~XLLP_USBOHCI_UHCRHDA_NPS;
pUsbhHandle->pUSBHRegs->UHCRHDA |= XLLP_USBOHCI_UHCRHDA_PSM;
// set the power management mode for each individual port to Per Port.
{
XLLP_UINT32_T p;
for( p = 0; p < NumPorts; p++ )
{
pUsbhHandle->pUSBHRegs->UHCRHDB |= (unsigned int)( 1u << (p+17) ); // port 1 begins at bit 17
}
}
break;
case XLLP_USBOHCI_PPM_MIXED:
// make sure the NO Power Switching mode bit is OFF so Power Switching can occur
// make sure the PSM bit is SET, which allows all ports to be controlled with
// the PER PORT set and clear power commands
pUsbhHandle->pUSBHRegs->UHCRHDA &= ~XLLP_USBOHCI_UHCRHDA_NPS;
pUsbhHandle->pUSBHRegs->UHCRHDA |= XLLP_USBOHCI_UHCRHDA_PSM;
// set the power management mode for each individual port to Per Port.
// if the value in the pPortMode array is non-zero, set Per Port mode for the port.
// if the value in the pPortMode array is zero, set Global mode for the port
{
XLLP_UINT32_T p;
for( p = 0; p < NumPorts; p++ )
{
if( pPortMode[p] )
{
pUsbhHandle->pUSBHRegs->UHCRHDB |= (unsigned int)( 1u << (p+17) ); // port 1 begins at bit 17
}
else
{
pUsbhHandle->pUSBHRegs->UHCRHDB &= ~(unsigned int)( 1u << (p+17) ); // port 1 begins at bit 17
}
}
}
break;
}
return (XLLP_USBH_SUCCESS);
}
/*******************************************************************************
*
* FUNCTION: XllpUsbhPowerUp
*
* DESCRIPTION: Called to power on USB Host at bootup and at resume from sleep
*
*
* INPUT PARAMETERS: P_XLLP_USBH_HANDLE_T pUsbhHandle
*
*
* RETURNS:
* Success: 0 (XLLP_USBH_SUCCESS)
* Failure:
*
* CALLS: XllpUsbhTurnOnUSBHostClock, XllpUsbhPortEnableOverCurrentNotification,
* XllpUsbhPortEnablePower, XllpUsbhSelectPowerManagementMode,
* XllpUsbhReset
*
* CALLED BY: HCD.
*
* PROTOTYPE: XLLP_USBH_ERROR_T XllpUsbhPowerUp(P_XLLP_USBH_HANDLE_T pUsbhHandle);
*
*
*******************************************************************************/
XLLP_USBH_ERROR_T XllpUsbhPowerUp(P_XLLP_USBH_HANDLE_T pUsbhHandle)
{
// make sure the ohci block is running (eg. getting clocked)
XllpUsbhTurnOnUSBHostClock(pUsbhHandle);
// this sets up Port 1 Pwr notification using gpio 88 as input in alternate function 1 mode
XllpUsbhPortEnableOverCurrentNotification(pUsbhHandle, XLLP_USBH_PORT_1);
// this sets up Port 1 Pwr enable using gpio 89 as output in alternate function 2 mode
XllpUsbhPortEnablePower(pUsbhHandle, XLLP_USBH_PORT_1);
XllpUsbhSelectPowerManagementMode(pUsbhHandle, XLLP_USBOHCI_PPM_NPS, 0, 0 );
XllpUsbhReset(pUsbhHandle);
return (XLLP_USBH_SUCCESS);
}
/*******************************************************************************
*
* FUNCTION: XllpUsbhPowerDown
*
* DESCRIPTION: Called to put USB Host into sleep mode
*
*
* INPUT PARAMETERS: P_XLLP_USBH_HANDLE_T pUsbhHandle
*
*
* RETURNS:
* Success: 0 (XLLP_USBH_SUCCESS)
* Failure:
*
* CALLS: XLLP_USBOHCI_UHCRHS_MWRITE
*
* CALLED BY: HCD.
*
* PROTOTYPE: XLLP_USBH_ERROR_T XllpUsbhPowerDown(P_XLLP_USBH_HANDLE_T pUsbhHandle);
*
*
*******************************************************************************/
XLLP_USBH_ERROR_T XllpUsbhPowerDown(P_XLLP_USBH_HANDLE_T pUsbhHandle)
{
//Check this whether its enough
//set global power switch mode
pUsbhHandle->pUSBHRegs->UHCRHDA &= ~ (XLLP_USBOHCI_UHCRHDA_NPS | XLLP_USBOHCI_UHCRHDA_PSM);
//Clear global power
XLLP_USBOHCI_UHCRHS_MWRITE( pUsbhHandle, XLLP_USBOHCI_UHCRHS_CGP);
return (XLLP_USBH_SUCCESS);
}
/*******************************************************************************
*
* FUNCTION: XllpUsbhPortEnableSleepStandbyEnable
*
* DESCRIPTION: Enable or disable power to the USB single-ended receivers
* and the USB port [1, 2 or 3] power supply
*
*
* INPUT PARAMETERS: P_XLLP_USBH_HANDLE_T pUsbhHandle
* XLLP_USBH_PORT_T Port - Port 1 (XLLP_USBH_PORT_1)
* or Port 2 (XLLP_USBH_PORT_2)
* or Port 3 (XLLP_USBH_PORT_3)
*
* RETURNS:
* Success: 0 (XLLP_USBH_SUCCESS)
* Failure:
*
* CALLS: None
*
* CALLED BY: XllpUsbhConfigPlatformSpecificUSBHReset
*
* PROTOTYPE: XLLP_USBH_ERROR_T XllpUsbhPortEnableSleepStandbyEnable(
* P_XLLP_USBH_HANDLE_T pUsbhHandle,
* XLLP_USBH_PORT_T Port,
* XLLP_BOOL_T enable);
*
*
*******************************************************************************/
XLLP_USBH_ERROR_T XllpUsbhPortEnableSleepStandbyEnable(P_XLLP_USBH_HANDLE_T pUsbhHandle,
XLLP_USBH_PORT_T Port,
XLLP_BOOL_T enable)
{
switch(Port)
{
case XLLP_USBH_PORT_1:
if (XLLP_TRUE == enable)
{
pUsbhHandle->pUSBHRegs->UHCHR &= ~XLLP_USBOHCI_UHCHR_SSEP1;
}
else
{
pUsbhHandle->pUSBHRegs->UHCHR |= XLLP_USBOHCI_UHCHR_SSEP1;
}
break;
case XLLP_USBH_PORT_2:
if (XLLP_TRUE == enable)
{
pUsbhHandle->pUSBHRegs->UHCHR &= ~XLLP_USBOHCI_UHCHR_SSEP2;
}
else
{
pUsbhHandle->pUSBHRegs->UHCHR |= XLLP_USBOHCI_UHCHR_SSEP2;
}
break;
case XLLP_USBH_PORT_3:
if (XLLP_TRUE == enable)
{
pUsbhHandle->pUSBHRegs->UHCHR &= ~XLLP_USBOHCI_UHCHR_SSEP3;
}
else
{
pUsbhHandle->pUSBHRegs->UHCHR |= XLLP_USBOHCI_UHCHR_SSEP3;
}
break;
}
return (XLLP_USBH_SUCCESS);
}
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