📄 xlli_dsplyfreqs.s
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A0_MEMCLK_ARRAY DCB "26 MHz", 0 ; L=0
ALIGN 16
DCB "26 MHz", 0 ; L=1
ALIGN 16
DCB "26 MHz", 0 ; L=2
ALIGN 16
DCB "39 MHz", 0 ; L=3
ALIGN 16
DCB "52 MHz", 0 ; L=4
ALIGN 16
DCB "65 MHz", 0 ; L=5
ALIGN 16
DCB "78 MHz", 0 ; L=6
ALIGN 16
DCB "91 MHz", 0 ; L=7
ALIGN 16
DCB "104 MHz", 0 ; L=8
ALIGN 16
DCB "117 MHz", 0 ; L=9
ALIGN 16
DCB "130 MHz", 0 ; L=10
ALIGN 16
DCB "71.5 MHz", 0 ; L=11
ALIGN 16
DCB "78 MHz", 0 ; L=12
ALIGN 16
DCB "84.5 MHz", 0 ; L=13
ALIGN 16
DCB "91 MHz", 0 ; L=14
ALIGN 16
DCB "97.5 MHz", 0 ; L=15
ALIGN 16
DCB "104 MHz", 0 ; L=16
ALIGN 16
DCB "110.5 MHz", 0 ; L=17
ALIGN 16
DCB "117 MHz", 0 ; L=18
ALIGN 16
DCB "124.5 MHz", 0 ; L=19
ALIGN 16
DCB "130 MHz", 0 ; L=20
ALIGN 16
DCB "68.25 MHz", 0 ; L=21
ALIGN 16
DCB "71.5 MHz", 0 ; L=22
ALIGN 16
DCB "74.75 MHz", 0 ; L=23
ALIGN 16
DCB "78 MHz", 0 ; L=24
ALIGN 16
DCB "81.25 MHz", 0 ; L=25
ALIGN 16
DCB "84.5 MHz", 0 ; L=26
ALIGN 16
DCB "87.75 MHz", 0 ; L=27
ALIGN 16
DCB "91 MHz", 0 ; L=28
ALIGN 16
DCB "94.25 MHz", 0 ; L=29
ALIGN 16
DCB "97.5 MHz", 0 ; L=30
ALIGN 16
DCB "100.75 MHz", 0 ; L=31
;----------------------------------------------------------------------------------------
;----------------------------------------------------------------------------------------
; Resume transmission code
;
ALIGN
A1_MemClk
;
; A=1, what does B equal?
;
mrc p14, 0, r2, c6, c0, 0 ; read CCLKCFG
ands r2, r2, #0x8 ; ne means bit set
bne B1_MemClk ; B=1
;
; B=0
;
add r2, pc, #A1B0_MEMCLK_ARRAY-(.+8) ; base adx of MEMCLK_ARRAY for A=1, B=0
add r2, r2, r6 ; Add index to base
xlli_PrintString r1, r2, r3 ; dump MEMCLK Freqency
b Done_MemClk
B1_MemClk
;
; B=1
;
add r2, pc, #A1B1_MEMCLK_ARRAY-(.+8) ; base adx of MEMCLK_ARRAY for A=1, B=1
add r2, r2, r6 ; Add index to base
xlli_PrintString r1, r2, r3 ; dump MEMCLK Freqency
Done_MemClk
b xlli_TXSDCLK
LTORG
;----------------------------------------------------------------------------------------
; This array is valid for A=1, B=0 frequencies
ALIGN 16
A1B0_MEMCLK_ARRAY DCB "13 MHz", 0 ; L=0
ALIGN 16
DCB "13 MHz", 0 ; L=1
ALIGN 16
DCB "13 MHz", 0 ; L=2
ALIGN 16
DCB "19.5 MHz", 0 ; L=3
ALIGN 16
DCB "26 MHz", 0 ; L=4
ALIGN 16
DCB "32.5 MHz", 0 ; L=5
ALIGN 16
DCB "39 MHz", 0 ; L=6
ALIGN 16
DCB "45.5 MHz", 0 ; L=7
ALIGN 16
DCB "52 MHz", 0 ; L=8
ALIGN 16
DCB "58.5 MHz", 0 ; L=9
ALIGN 16
DCB "65 MHz", 0 ; L=10
ALIGN 16
DCB "71.5 MHz", 0 ; L=11
ALIGN 16
DCB "78 MHz", 0 ; L=12
ALIGN 16
DCB "84.5 MHz", 0 ; L=13
ALIGN 16
DCB "91 MHz", 0 ; L=14
ALIGN 16
DCB "97.5 MHz", 0 ; L=15
ALIGN 16
DCB "104 MHz", 0 ; L=16
ALIGN 16
DCB "110.5 MHz", 0 ; L=17
ALIGN 16
DCB "117 MHz", 0 ; L=18
ALIGN 16
DCB "124.5 MHz", 0 ; L=19
ALIGN 16
DCB "130 MHz", 0 ; L=20
ALIGN 16
DCB "136.5 MHz", 0 ; L=21
ALIGN 16
DCB "143 MHz", 0 ; L=22
ALIGN 16
DCB "149.5 MHz", 0 ; L=23
ALIGN 16
DCB "156 MHz", 0 ; L=24
ALIGN 16
DCB "162.5 MHz", 0 ; L=25
ALIGN 16
DCB "169 MHz", 0 ; L=26
ALIGN 16
DCB "175.5 MHz", 0 ; L=27
ALIGN 16
DCB "182 MHz", 0 ; L=28
ALIGN 16
DCB "188.5 MHz", 0 ; L=29
ALIGN 16
DCB "195 MHz", 0 ; L=30
ALIGN 16
DCB "201.5 MHz", 0 ; L=31
; This array is valid for A=1, B=1 frequencies
ALIGN 16
A1B1_MEMCLK_ARRAY DCB "26 MHz", 0 ; L=0
ALIGN 16
DCB "26 MHz", 0 ; L=1
ALIGN 16
DCB "26 MHz", 0 ; L=2
ALIGN 16
DCB "39 MHz", 0 ; L=3
ALIGN 16
DCB "52 MHz", 0 ; L=4
ALIGN 16
DCB "65 MHz", 0 ; L=5
ALIGN 16
DCB "78 MHz", 0 ; L=6
ALIGN 16
DCB "91 MHz", 0 ; L=7
ALIGN 16
DCB "104 MHz", 0 ; L=8
ALIGN 16
DCB "117 MHz", 0 ; L=9
ALIGN 16
DCB "130 MHz", 0 ; L=10
ALIGN 16
DCB "143 MHz", 0 ; L=11
ALIGN 16
DCB "156 MHz", 0 ; L=12
ALIGN 16
DCB "169 MHz", 0 ; L=13
ALIGN 16
DCB "182 MHz", 0 ; L=14
ALIGN 16
DCB "195 MHz", 0 ; L=15
ALIGN 16
DCB "208 MHz", 0 ; L=16
;; For L > 16, we (in XLLI) force B=0.
;----------------------------------------------------------------------------------------
;----------------------------------------------------------------------------------------
; Resume transmission code
;
ALIGN
xlli_TXSDCLK
;
; Tx B setting
;
mrc p14, 0, r6, c6, c0, 0 ; read CCLKCFG
ands r6, r6, #0x8 ; ne means bit set
addne r2, pc, #FASTBUSMODE-(.+8)
addeq r2, pc, #NORMALBUSMODE-(.+8)
xlli_PrintString r1, r2, r3
;
; Tx the SDCLK[1] setting (SDRAM clk)
;
ldr r1, =xlli_MEMORY_CONFIG_BASE
ldr r2, [r1, #xlli_MDREFR_offset] ; read MDREFR
ands r2, r2, #0x20000 ; check K1DB2
addne r2, pc, #SDCLK_HALF_MSG-(.+8) ; K1DB2 SET (run SDCLK= .5(MemClk))
addeq r2, pc, #SDCLK_EQU_MSG-(.+8) ; K1DB2 CLEAR (run SDCLK= MemClk)
ldr r1, =xlli_Target_UART
xlli_PrintString r1, r2, r3 ; Tx the SDCLK[1] setting
;
; Tx the SDCLK[0] setting (Sync FLASH clk)
;
ldr r1, =xlli_MEMORY_CONFIG_BASE
ldr r3, [r1, #xlli_MDREFR_offset] ; read MDREFR
ands r2, r3, #0x4000 ; check K0DB2
addne r2, pc, #SDCLK0_HALF_MSG-(.+8) ; K0DB2 SET (potentially running SDCLK0= MemClk/2)
addeq r2, pc, #SDCLK0_EQU_MSG-(.+8) ; K0DB2 CLEAR (potentially running SDCLK0= MemClk)
ands r3, r3, #0x20000000 ; check K0DB4... if set, will override k0db2
addne r2, pc, #SDCLK0_QUARTER_MSG-(.+8) ; K0DB4 SET (run SDCLK0= .25(MemClk))
ldr r1, =xlli_Target_UART
xlli_PrintString r1, r2, r3 ; Tx the SDCLK[1] setting
;
; display Run vs. Turbo Mode
;
xlli_ret_ClkCfg r6 ; cp14.6[3:0] in r6
ands r6, r6, #1
addne r2, pc, #TURBOMODE-(.+8)
addeq r2, pc, #RUNMODE-(.+8)
ldr r1, =xlli_Target_UART ; Tx the setting
xlli_PrintString r1, r2, r3
;
; Tx whether L18 in Sync or Async mode
; Do this be examining SXCFNG.SXEN0[0]
;
ldr r1, =xlli_MEMORY_CONFIG_BASE
ldr r3, [r1, #xlli_SXCNFG_offset] ; read sxcnfg
ands r3, r3, #1
addne r2, pc, #SYNC_FLASH_ON_MSG-(.+8)
addeq r2, pc, #SYNC_FLASH_OFF_MSG-(.+8)
ldr r1, =xlli_Target_UART
xlli_PrintString r1, r2, r3 ; Tx the SDCLK[1] setting
END_DISPLAY
mov pc, lr ; Return to the calling function
LTORG
;----------------------------------------------------------------------------------------
;
; Bus Mode Banners
;
ALIGN
FASTBUSMODE DCB 0xA,0xD, "Bus Mode = FAST", 0xA, 0xD, 0
ALIGN
NORMALBUSMODE DCB 0xA,0xD, "Bus Mode = NORMAL", 0xA, 0xD, 0
;
; SDCLK[1] Banners
;
ALIGN
SDCLK_HALF_MSG DCB "SDCLK[1] = MemClk/2 (SDRAM Clk)", 0xA, 0xD, 0
ALIGN
SDCLK_EQU_MSG DCB "SDCLK[1] = MemClk (SDRAM Clk)", 0xA, 0xD, 0
;
; SDCLK[0] Banners
;
ALIGN
SDCLK0_QUARTER_MSG DCB "SDCLK[0] = MemClk/4 (Sync. FLASH Clk)", 0xA, 0xD, 0
ALIGN
SDCLK0_HALF_MSG DCB "SDCLK[0] = MemClk/2 (Sync. FLASH Clk)", 0xA, 0xD, 0
ALIGN
SDCLK0_EQU_MSG DCB "SDCLK[0] = MemClk (Sync. FLASH Clk)", 0xA, 0xD, 0
;
; Flash Mode Banners
;
ALIGN
SYNC_FLASH_OFF_MSG DCB "Boot FLASH in Asynchronous mode", 0xA, 0xD, 0
ALIGN
SYNC_FLASH_ON_MSG DCB "Boot FLASH in Synchronous mode", 0xA, 0xD, 0
;
; Run/Turbo Mode Banners
;
ALIGN
RUNMODE DCB "Mode = RUN", 0xA, 0xD, 0xA, 0xD, 0
ALIGN
TURBOMODE DCB "Mode = TURBO", 0xA, 0xD, 0xA, 0xD, 0
;----------------------------------------------------------------------------------------
ENDFUNC
;----------------------------------------------------------------------------------------
;----------------------------------------------------------------------------------------
END
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