📄 xlli_dsplyfreqs.s
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;----------------------------------------------------------------------------------------
; INTEL CONFIDENTIAL
; Copyright 2002-2004 Intel Corporation All Rights Reserved.
;
; The source code contained or described herein and all documents
; related to the source code (Material) are owned by Intel Corporation
; or its suppliers or licensors. Title to the Material remains with
; Intel Corporation or its suppliers and licensors. The Material contains
; trade secrets and proprietary and confidential information of Intel
; or its suppliers and licensors. The Material is protected by worldwide
; copyright and trade secret laws and treaty provisions. No part of the
; Material may be used, copied, reproduced, modified, published, uploaded,
; posted, transmitted, distributed, or disclosed in any way without Intel's
; prior express written permission.
;
; No license under any patent, copyright, trade secret or other intellectual
; property right is granted to or conferred upon you by disclosure or
; delivery of the Materials, either expressly, by implication, inducement,
; estoppel or otherwise. Any license under such intellectual property rights
; must be express and approved by Intel in writing.
;
;
;----------------------------------------------------------------------------------------
;
; FILENAME: xlli_dsplyfreqs.s
;
; PURPOSE: Provides low Level routines to display processor stepping,
; current frequencies, etc. to the serial port
;
; LAST MODIFIED: 6-Oct-2004
;
;----------------------------------------------------------------------------------------
;
; The functions in this source code are using the branch with link instruction.
; Unless otherwise specified, no system stack is assumed and no registers are preserved.
;
; NOTES:
;
;
;----------------------------------------------------------------------------------------
INCLUDE xlli_Bulverde_defs.inc ; PXA27x specific include file
INCLUDE xlli_Mainstone_defs.inc ; Mainstone specific include file
INCLUDE xlli_LowLev_mac.mac ; Mainstone Macro definitions
AREA |text|, CODE, READONLY, ALIGN=5 ; Align =5 required for "ALIGN 32" feature to work.
;
; List of Low Level Init functions in this source code include:
;
EXPORT xlli_display_frequencies ; Dumps the settings to the serial port
;----------------------------------------------------------------------------------------
;
; *********************************************************
; ********** **********
; ********** xlli_display_frequencies **********
; ********** **********
; *********************************************************
;
; This subroutine will read the system configuration for the Memory controller, CPU ID
; and Clock configuration and display to the UART choosen above
;
; Notes:
;
; This subroutine uses and DOES NOT PRESERVE registers r1, r2, r3, r4, r5, r6
;
xlli_display_frequencies FUNCTION
;
; Load the CPU ID value into R5 for future use
;
mrc p15, 0, r5, c0, c0, 0 ; Grab CPU ID again for banners
;
; Tx a banner
;
ldr r1, =xlli_Target_UART
xlli_InitUART r1, r2
add r2, pc, #BANNER-(.+8)
xlli_PrintString r1, r2, r3 ; Tx a simple Banner
;
; Tx the Processor stepping
;
ldr r4, =xlli_PXA27x_CP15_A0_Val ; load R4 with value
cmp r5, r4 ; Compare
addeq r2, pc, #A0_PXA27X_BNR-(.+8) ; Running A0 PXA27x
beq %F5 ; Transmit
ldr r4, =xlli_PXA27x_CP15_A1_Val ; load R4 with value
cmp r5, r4 ; Compare
addeq r2, pc, #A1_PXA27X_BNR-(.+8) ; Running A1 PXA27x
beq %F5 ; Transmit
ldr r4, =xlli_PXA27x_CP15_B0_Val ; load R4 with value
cmp r5, r4 ; Compare
addeq r2, pc, #B0_PXA27X_BNR-(.+8) ; Running B0 PXA27x
beq %F5 ; Transmit
ldr r4, =xlli_PXA27x_CP15_B1_Val ; load R4 with value
cmp r5, r4 ; Compare
addeq r2, pc, #B1_PXA27X_BNR-(.+8) ; Running B1 PXA27x
beq %F5 ; Transmit
ldr r4, =xlli_PXA27x_CP15_C0_Val ; load R4 with value
cmp r5, r4 ; Compare
addeq r2, pc, #C0_PXA27X_BNR-(.+8) ; Running C0 PXA27x
beq %F5 ; Transmit
ldr r4, =xlli_PXA27x_CP15_C5_Val ; load R4 with value
cmp r5, r4 ; Compare
addeq r2, pc, #C5_PXA27X_BNR-(.+8) ; Running C7 PXA27x
beq %F5 ; Transmit
5
ldr r1, =xlli_Target_UART ; Tx Processor Stepping
xlli_PrintString r1, r2, r3
;
; Tx Run Mode Frequency
;
ldr r3, =xlli_CLKREGS_PHYSICAL_BASE
xlli_retCCSR_L_Val r6, r3, r2 ; r6 gets the value in CCSR_L
mov r6, r6, LSL #3 ; L := L*8 = index into RUNMODE_ARRAY
add r2, pc, #RUNMODESTR-(.+8) ; dump "Run Mode = " banner
xlli_PrintString r1, r2, r3
add r2, pc, #RUNMODE_ARRAY-(.+8) ; base adx of RUNMODE_ARRAY
add r2, r2, r6 ; Add index to base
xlli_PrintString r1, r2, r3 ; dump Run Mode Freqency
;
; Tx Turbo Mode Frequency
;
ldr r3, =xlli_CLKREGS_PHYSICAL_BASE
xlli_retCCSR_2N_Val r6, r3, r2 ; r6 gets the value in CCSR_2N (2,3,4,5 or 6)
cmp r6, #2
addeq r2, pc, #N_1-(.+8)
cmp r6, #3
addeq r2, pc, #N_15-(.+8)
cmp r6, #4
addeq r2, pc, #N_2-(.+8)
cmp r6, #5
addeq r2, pc, #N_25-(.+8)
cmp r6, #6
addeq r2, pc, #N_3-(.+8)
cmp r6, #7
addeq r2, pc, #N_35-(.+8)
cmp r6, #8
addeq r2, pc, #N_4-(.+8)
;
; Dump the banner
;
xlli_PrintString r1, r2, r3
;
; Tx the MemClk banner
;
add r2, pc, #MEMCLKSTR-(.+8) ; dump "MemClk = " banner
xlli_PrintString r1, r2, r4
b xlli_TXMEM
LTORG
;----------------------------------------------------------------------------------------
;----------------------------------------------------------------------------------------
; Processor IDs used for UART Transmissions
;----------------------------------------------------------------------------------------
ALIGN
BANNER DCB 0xA, 0xD, 0xA, 0xD, "*******Beginning System Initialization*******", 0xA, 0xD, 0
ALIGN
A0_PXA27X_BNR DCB 0xA, 0xD, "CPU ID = A0 PXA27x", 0xA, 0xD, 0
ALIGN
A1_PXA27X_BNR DCB 0xA, 0xD, "CPU ID = A1 PXA27x", 0xA, 0xD, 0
ALIGN
B0_PXA27X_BNR DCB 0xA, 0xD, "CPU ID = B0 PXA27x", 0xA, 0xD, 0
ALIGN
B1_PXA27X_BNR DCB 0xA, 0xD, "CPU ID = B1 PXA27x", 0xA, 0xD, 0
ALIGN
C0_PXA27X_BNR DCB 0xA, 0xD, "CPU ID = C0 PXA27x", 0xA, 0xD, 0
ALIGN
C5_PXA27X_BNR DCB 0xA, 0xD, "CPU ID = C5 PXA27x", 0xA, 0xD, 0
;----------------------------------------------------------------------------------------
ALIGN 16
RUNMODE_ARRAY
DCB "26 MHz", 0 ; L=0
ALIGN 8
DCB "26 MHz", 0 ; L=1
ALIGN 8
DCB "26 MHz", 0 ; L=2
ALIGN 8
DCB "39 MHz", 0 ; L=3
ALIGN 8
DCB "52 MHz", 0 ; L=4
ALIGN 8
DCB "65 MHz", 0 ; L=5
ALIGN
DCB "78 MHz", 0 ; L=6
ALIGN
DCB "91 MHz", 0 ; L=7
ALIGN
DCB "104 MHz", 0 ; L=8
ALIGN
DCB "117 MHz", 0 ; L=9
ALIGN
DCB "130 MHz", 0 ; L=10
ALIGN
DCB "143 MHz", 0 ; L=11
ALIGN
DCB "156 MHz", 0 ; L=12
ALIGN
DCB "169 MHz", 0 ; L=13
ALIGN
DCB "182 MHz", 0 ; L=14
ALIGN
DCB "195 MHz", 0 ; L=15
ALIGN
DCB "208 MHz", 0 ; L=16
ALIGN
DCB "221 MHz", 0 ; L=17
ALIGN
DCB "234 MHz", 0 ; L=18
ALIGN
DCB "247 MHz", 0 ; L=19
ALIGN
DCB "260 MHz", 0 ; L=20
ALIGN
DCB "273 MHz", 0 ; L=21
ALIGN
DCB "286 MHz", 0 ; L=22
ALIGN
DCB "299 MHz", 0 ; L=23
ALIGN
DCB "312 MHz", 0 ; L=24
ALIGN
DCB "325 MHz", 0 ; L=25
ALIGN
DCB "338 MHz", 0 ; L=26
ALIGN
DCB "351 MHz", 0 ; L=27
ALIGN
DCB "364 MHz", 0 ; L=28
ALIGN
DCB "377 MHz", 0 ; L=29
ALIGN
DCB "390 MHz", 0 ; L=30
ALIGN
DCB "403 MHz", 0 ; L=31
;----------------------------------------------------------------------------------------
;
; Run mode Banners
;
ALIGN
RUNMODESTR DCB "Run Mode = ", 0
;
; CCCR[N] Banners
;
ALIGN
N_1 DCB 0xA, 0xD, "Turbo Mode = Run Mode", 0xA, 0xD, 0
ALIGN
N_15 DCB 0xA, 0xD, "Turbo Mode = 1.5 * Run Mode", 0xA, 0xD, 0
ALIGN
N_2 DCB 0xA, 0xD, "Turbo Mode = 2 * Run Mode", 0xA, 0xD, 0
ALIGN
N_25 DCB 0xA, 0xD, "Turbo Mode = 2.5 * Run Mode", 0xA, 0xD, 0
ALIGN
N_3 DCB 0xA, 0xD, "Turbo Mode = 3 * Run Mode", 0xA, 0xD, 0
ALIGN
N_35 DCB 0xA, 0xD, "Turbo Mode = 3.5 * Run Mode", 0xA, 0xD, 0
ALIGN
N_4 DCB 0xA, 0xD, "Turbo Mode = 4 * Run Mode", 0xA, 0xD, 0
;----------------------------------------------------------------------------------------
;
; MemClk Banners
;
ALIGN
MEMCLKSTR DCB 0xA, 0xD, "MemClk = ", 0
;----------------------------------------------------------------------------------------
;----------------------------------------------------------------------------------------
; Resume transmission code
;
ALIGN
xlli_TXMEM
;
; Tx Corresponding MEMCLK, based on L
;
ldr r3, =xlli_CLKREGS_PHYSICAL_BASE
xlli_retCCSR_L_Val r6, r3, r2 ; r6 gets the value in CCSR_L
mov r6, r6, LSL #4 ; L := L*16 = index into MEMCLK_ARRAY
;
; Grab the A bit so know which
;
ldr r2, [r3, #xlli_CCSR_offset]
ldr r3, =0x02000000
ands r2, r2, r3 ; Get bit 25 (A-bit),
bne A1_MemClk ; ne means bit set
;
; A=0
;
add r2, pc, #A0_MEMCLK_ARRAY-(.+8) ; base adx of MEMCLK_ARRAY for A=0
add r2, r2, r6 ; Add index to base
xlli_PrintString r1, r2, r3 ; dump MEMCLK Freqency
b Done_MemClk ; Done printing MemClk
LTORG
;----------------------------------------------------------------------------------------
; This array is valid for all A=0 frequencies.
ALIGN 16
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