xllp_lcd.c

Intel PXA270底层设备驱动代码

		LCLK = (13 * CCCR_L) * 100;
	else if (CCCR_L < 17) // L = [8 - 16] 
		LCLK = ((13 * CCCR_L) * 100) >> 1;
	else if (CCCR_L < 32) // L = [17 - 31]
		LCLK = ((13 * CCCR_L) * 100) >> 2;
		
	
	// Convert the bpp setting into a value that the LCD controller understands.
	switch(pXllpLCD->BPP)
	{
		case BPP_1:
			BPP = 0;
			break;
		case BPP_2:
			BPP = 1;
			break;
		case BPP_4:
			BPP = 2;
			break;
		case BPP_8:
			BPP = 3;
			break;
		case BPP_16:
			BPP = 4;
			break;
		case BPP_18:
			BPP = 5;
			break;
		case BPP_18_PACKED:
			BPP = 6;
			break;
		case BPP_19:
			BPP = 7;
			break;
		case BPP_19_PACKED:
			BPP = 8;
			break;
		case BPP_24:
			BPP = 9;
			break;
		case BPP_25:
			BPP = 10;
			break;
		default:
		{
			BPP = 0;
			break;
		}
	}

	switch(pXllpLCD->DisplayType)
	{
    	case LTM04C380K: // 640x480 16bpp active matrix
		{

			// 
			// The actual equation requires that we take the ceiling of a floating point result.
			// Rather than use floats, we'll calculate an approximation to the correct PCD value
			// using integers.  
			//
			PCD = (LCLK / (2 * LTM04C380K_PIXEL_CLOCK_FREQUENCY));

			// Configure the LCD Controller Control Registers
			p_LCDRegs->LCCR0 = (LCD_LDM | LCD_SFM | LCD_IUM | LCD_EFM | 
								LCD_PAS | LCD_QDM | LCD_BM  | LCD_OUM |
								LCD_RDSTM | LCD_CMDIM | LCD_OUC | LCD_LDDALT);

			p_LCDRegs->LCCR1 = (LCD_PPL(0x27FU) | LCD_HSW(0x01) | 
								LCD_ELW(0x01)  | LCD_BLW(0x9fU) );
			
			p_LCDRegs->LCCR2 = (LCD_LPP(0x1df) | LCD_VSW(0x2c) |
								LCD_EFW(0x00)  | LCD_BFW(0x00) );

			p_LCDRegs->LCCR3 = (LCD_PCD(PCD)  | LCD_BPP(BPP) | LCD_PCP |
								LCD_PDFOR(pXllpLCD->PixelDataFormat));
			
			p_LCDRegs->LCCR4 = LCD_PAL_FOR(0);
			if ( (p_LCDRegs->OVL1C1 & LCD_O1EN) || (p_LCDRegs->OVL2C1 & LCD_O2EN))
			{
				p_LCDRegs->LCCR4 = LCD_PAL_FOR(1);
			}
		}
		break;

    case LTM035A776C: // 240x320 16bpp active matrix
		{

			// 
			// The actual equation requires that we take the ceiling of a floating point result.
			// Rather than use floats, we'll calculate an approximation to the correct PCD value
			// using integers.
			//
			PCD = (LCLK / (2 * LTM035A776C_PIXEL_CLOCK_FREQUENCY));
			
			// Configure the LCD Controller Control Registers
			p_LCDRegs->LCCR0 = (LCD_LDM | LCD_SFM | LCD_IUM | LCD_EFM | 
								LCD_PAS | LCD_QDM | LCD_BM  | LCD_OUM |
								LCD_RDSTM | LCD_CMDIM | LCD_OUC | LCD_LDDALT);

			p_LCDRegs->LCCR1 = (LCD_PPL(0xEF) | LCD_HSW(0x04) | 
								LCD_ELW(0x04)  | LCD_BLW(0x05) );
			
			p_LCDRegs->LCCR2 = (LCD_LPP(0x13f) | LCD_VSW(0x02) |
								LCD_EFW(0x03)  | LCD_BFW(0x02) );

			p_LCDRegs->LCCR3 = (LCD_PCD(PCD)  | LCD_BPP(BPP) | LCD_PCP | LCD_HSP |
								LCD_PDFOR(pXllpLCD->PixelDataFormat));
			
			p_LCDRegs->LCCR4 = LCD_PAL_FOR(0);
			if ( (p_LCDRegs->OVL1C1 & LCD_O1EN) || (p_LCDRegs->OVL2C1 & LCD_O2EN))
			{
				p_LCDRegs->LCCR4 = LCD_PAL_FOR(1);
			}

			// LCD senses 13M mode and sets PCD to SENSE_MD_PCD automatically
			p_LCDRegs->LCCR4 |= LCD_SENSE_PCD_CHG_EN | LCD_SENSE_MD_PCD(1);
		}
		break;

    case LM8V31: // 640x480 16bpp dual panel passive
		{

			// 
			// The actual equation requires that we take the ceiling of a floating point result.
			// Rather than use floats, we'll calculate an approximation to the correct PCD value
			// using integers.
			//
			PCD = (LCLK / (2 * LM8V31_PIXEL_CLOCK_FREQUENCY));

			// Reconfigure the upper panel frame descriptors for dual panel operation by
			// setting the DMA transfer length to half the size of the frame buffer
			pXllpLCD->frameDescriptorCh0fd1->LDCMD = pXllpLCD->FrameBufferSize >> 1;
			pXllpLCD->frameDescriptorCh0fd2->LDCMD = pXllpLCD->FrameBufferSize >> 1;

			// Configure the lower panel frame descriptor for dual panel operation.
			// Set the physical address of the frame descriptor
			pXllpLCD->frameDescriptorCh1->FDADR = LCD_FDADR(pXllpLCD->_DMA_CHANNEL_1_FRAME_DESCRIPTOR_BASE_PHYSICAL);

			// Set the physical address of the frame buffer
			pXllpLCD->frameDescriptorCh1->FSADR = LCD_FSADR(pXllpLCD->_FRAME_BUFFER_BASE_PHYSICAL + pXllpLCD->CurrentPage*pXllpLCD->FrameBufferSize + (pXllpLCD->FrameBufferSize >> 1));

			// Clear the frame ID
			pXllpLCD->frameDescriptorCh1->FIDR  = LCD_FIDR(0);

			// Set the DMA transfer length to half the size of the frame buffer
			pXllpLCD->frameDescriptorCh1->LDCMD = LCD_Len(pXllpLCD->FrameBufferSize >> 1);

			// Store the physical address of this frame descriptor in the frame descriptor
			pXllpLCD->frameDescriptorCh1->PHYSADDR = pXllpLCD->frameDescriptorCh1->FDADR;
			
			// FBR1 is cleared and is not used in this implementation
			p_LCDRegs->FBR1 = 0;

			// Load the contents of FDADR1 with the physical address of this frame descriptor
			p_LCDRegs->FDADR1 = pXllpLCD->frameDescriptorCh1->FDADR;
		
			
			// Configure the TMED dithering engine
			// Use the magic number described in the EAS, 0x00AA5500;
			p_LCDRegs->TRGBR = LCD_TRS(0x00) | LCD_TGS(0x55) | LCD_TBS(0xAA);

			// Use the magic number described in the EAS, 0x0000754F;
			p_LCDRegs->TCR = LCD_TM2S | LCD_TM1S | LCD_TM2En | LCD_TM1En		|
							 LCD_TVBS(0x04) | LCD_THBS(0x05) | LCD_TSCS(0x03)	|  
							 LCD_TED;

		
			p_LCDRegs->LCCR0 = (LCD_SDS | LCD_LDM | LCD_SFM | LCD_IUM	|
								LCD_EFM | LCD_PDD(0x01)		| LCD_BM	|
								LCD_RDSTM | LCD_CMDIM | LCD_OUC | LCD_LDDALT);

			p_LCDRegs->LCCR1 = (LCD_PPL(0x27F)	| LCD_HSW(0x02) |
								LCD_ELW(0x03)	| LCD_BLW(0x03) );

			p_LCDRegs->LCCR2 = (LCD_LPP(0xef)	| LCD_VSW(0x01) |
								LCD_EFW(0x00)	| LCD_BFW(0x00) );

			p_LCDRegs->LCCR3 = (LCD_PCD(PCD)	| LCD_ACB(0xff) |
								LCD_PCP			| LCD_BPP(BPP)  |
								LCD_PDFOR(pXllpLCD->PixelDataFormat));

			p_LCDRegs->LCCR4 = LCD_PAL_FOR(0);
			if ( (p_LCDRegs->OVL1C1 & LCD_O1EN) || (p_LCDRegs->OVL2C1 & LCD_O2EN))
			{
				p_LCDRegs->LCCR4 = LCD_PAL_FOR(1);
			}
        }
		break;
    case LQ64D341: // 176x220 active matrix Stinger display
		{

			// 
			// The actual equation requires that we take the ceiling of a floating point result.
			// Rather than use floats, we'll calculate an approximation to the correct PCD value
			// using integers.
			//
			PCD = (LCLK / (2 * LQ64D341_PIXEL_CLOCK_FREQUENCY));

			p_LCDRegs->LCCR0 = ( LCD_LDM | LCD_SFM | LCD_IUM	|
								 LCD_EFM | LCD_PAS | LCD_BM		|
								 LCD_RDSTM | LCD_CMDIM | LCD_OUC | LCD_LDDALT);

			p_LCDRegs->LCCR1 = ( LCD_PPL(0xAF)	| LCD_HSW(0x02) |
								 LCD_ELW(0x7B)	| LCD_BLW(0x03) );

			p_LCDRegs->LCCR2 = ( LCD_LPP(0xdb)	| LCD_VSW(0x01) |
								 LCD_EFW(0x02)	| LCD_BFW(0x00) );

			p_LCDRegs->LCCR3 = ( LCD_PCD(PCD)	| LCD_BPP(BPP)	 | 
								 LCD_VSP		| LCD_HSP		 | LCD_PCP  | 
								 LCD_OEP		| LCD_PDFOR(pXllpLCD->PixelDataFormat));

			p_LCDRegs->LCCR4 = LCD_PAL_FOR(0);
			if ( (p_LCDRegs->OVL1C1 & LCD_O1EN) || (p_LCDRegs->OVL2C1 & LCD_O2EN))
			{
				p_LCDRegs->LCCR4 = LCD_PAL_FOR(1);
			}

        	}
		break;

	case LS022Q8DD06: // Sharp LS022Q8DD06 Sharp 240 x 320 for ZOAR
		{
			// 
			// The actual equation requires that we take the ceiling of a floating point result.
			// Rather than use floats, we'll calculate an approximation to the correct PCD value
			// using integers.
			//

			PCD = (LCLK / (2 * LS022Q8DD06_PIXEL_CLOCK_FREQUENCY));

			// Configure the LCD Controller Control Registers
			p_LCDRegs->LCCR0 = (LCD_LDM | LCD_SFM | LCD_IUM | LCD_EFM | 
						LCD_PAS | LCD_QDM | LCD_BM  | LCD_OUM |
						LCD_RDSTM | LCD_CMDIM | LCD_OUC | LCD_LDDALT);

			p_LCDRegs->LCCR1 = (LCD_PPL(0xEF) | LCD_HSW(0x01) | 
						LCD_ELW(0x00)  | LCD_BLW(0x07) );
			
			p_LCDRegs->LCCR2 = (LCD_LPP(0x13f) | LCD_VSW(0x02) |
						LCD_EFW(0x02)  | LCD_BFW(0x00) );

			p_LCDRegs->LCCR3 = (LCD_PCD(PCD)  | LCD_BPP(BPP) | LCD_PCP | 
						LCD_PDFOR(pXllpLCD->PixelDataFormat));
			
			p_LCDRegs->LCCR4 = LCD_PAL_FOR(0);
			if ( (p_LCDRegs->OVL1C1 & LCD_O1EN) || (p_LCDRegs->OVL2C1 & LCD_O2EN))
			{
				p_LCDRegs->LCCR4 = LCD_PAL_FOR(1);
			}

//			XllpLock(XLLP_RESOURCE_CKEN);
			p_CLKRegs->cken = (p_CLKRegs->cken & XLLP_CLKEN_MASK) | CLK_SSP3;
//			XllpUnlock(XLLP_RESOURCE_CKEN);

			// Assert chip select on the LCD
//			XllpLock(XLLP_RESOURCE_GPCR2);
//			XllpLock(XLLP_RESOURCE_GPSR2);
			
			p_GPIORegs->GPSR2 = XLLP_GPIO_BIT_L_BIAS;	
	
			XllpOstDelayMilliSeconds(p_OSTRegs, 1);
			p_SSPRegs->sscr0 = 0x00C01030;
			p_SSPRegs->sscr1 = 0x00008000;
			p_SSPRegs->sspsp = 0x0025000C;
			p_SSPRegs->sscr0 |= 0x8F;

			// Wait for the operation to complete
			while(p_SSPRegs->sssr & 0x10);

			for (i = 0; i < sizeof(LS022Q8DD06_DATA_SET_1) >> 1; i+=2)
			{
				p_GPIORegs->GPSR2 = XLLP_GPIO_BIT_L_BIAS;	
	
				p_SSPRegs->ssdr = LS022Q8DD06_DATA_SET_1[i];
				p_SSPRegs->ssdr = LS022Q8DD06_DATA_SET_1[i+1];

				// Wait for the operation to complete
				while(p_SSPRegs->sssr & 0x10);
	
				XllpOstDelayMicroSeconds(p_OSTRegs, 50);
				p_GPIORegs->GPCR2 = XLLP_GPIO_BIT_L_BIAS;

				XllpOstDelayMilliSeconds(p_OSTRegs, 100);
			}

			for (i = 0; i < sizeof(LS022Q8DD06_DATA_SET_2) >> 1; i+=2)
			{
				p_GPIORegs->GPSR2 = XLLP_GPIO_BIT_L_BIAS;	
	
				p_SSPRegs->ssdr = LS022Q8DD06_DATA_SET_2[i];
				p_SSPRegs->ssdr = LS022Q8DD06_DATA_SET_2[i+1];

				// Wait for the operation to complete
				while(p_SSPRegs->sssr & 0x10);
				XllpOstDelayMicroSeconds(p_OSTRegs, 50);
				p_GPIORegs->GPCR2 = XLLP_GPIO_BIT_L_BIAS;
			
				XllpOstDelayMilliSeconds(p_OSTRegs, 100);
			}


			// De-assert chip select on the LCD
			p_GPIORegs->GPCR2 = XLLP_GPIO_BIT_L_BIAS;
//			XllpUnlock(XLLP_RESOURCE_GPCR2);
//			XllpUnlock(XLLP_RESOURCE_GPSR2);

            //
            // Ensure GPIO writes that have posted complete
            //
            APB_Temp = p_GPIORegs->GAFR0_L;

		}
		break;

	default:
		{

		}
		break;
	}

}