startup.s

Intel DBPXA27X评估板OAL层代码.

;
; Copyright (c) Microsoft Corporation.  All rights reserved.
;
;
; Use of this source code is subject to the terms of the Microsoft end-user
; license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
; If you did not accept the terms of the EULA, you are not authorized to use
; this source code. For a copy of the EULA, please see the LICENSE.RTF on your
; install media.
;
;------------------------------------------------------------------------------
;
;   File:  startup.s
;
;   Kernel startup routine for the Intel Mainstone II board.
;
;------------------------------------------------------------------------------

    INCLUDE kxarm.h
    INCLUDE bulverde.inc
    INCLUDE mainstoneii.inc
    INCLUDE xlli_Bulverde_defs.inc
    INCLUDE xlli_Mainstone_defs.inc
    
    INCLUDE image_cfg.inc         ; IMAGE_SHARE_ARGS address and size
    INCLUDE args.inc              ; RESTART_DATA and BOOT_STACK addresses and sizes
    INCLUDE xllp_restart_data.inc ; RESTART_DATA detailed definition
    
    IMPORT  KernelStart

;------------------------------------------------------------------------
    TEXTAREA
    
;------------------------------------------------------------------------
; Pause N Milliseconds - BE WARNED OF THE REGISTER ASSUMPTIONS!
;------------------------------------------------------------------------
    MACRO
    BL_PAUSE $ms
        ldr     r1,  =$ms                        ; # milliseconds
        cmp     r1, #0
        beq     %F3
        cmp     r1, #0xffffffff
1
        beq     %B1

        ldr     r0,  =xlli_OSTREGS_PHYSICAL_BASE ; Load OS timer base address
        ldr     r0,  [r0, #xlli_OSCR0_offset]    ; Fetch starting value of OSCR0
        ldr     r1,  =3250*$ms                   ; # miliseconds (3250 per XLLP_OST_TICKS_MS)
        add     r1,  r0, r1
2
        ldr     r0,  =xlli_OSTREGS_PHYSICAL_BASE ; Load OS timer base address
        ldr     r0,  [r0, #xlli_OSCR0_offset]    ; Fetch starting value of OSCR0
        cmp     r0,  r1                          ; Is the timer past the time out value?
        bmi     %B2                              ; No - Loop until it is
3
    MEND

;------------------------------------------------------------------------
; HEX LED Macros - BE WARNED OF THE REGISTER ASSUMPTIONS!
;------------------------------------------------------------------------

BL_SHL_NOWAIT       EQU 0
BL_SHL_SHORTWAIT    EQU 2000
BL_SHL_MEDWAIT      EQU BL_SHL_SHORTWAIT*2
BL_SHL_LONGWAIT     EQU BL_SHL_SHORTWAIT*3

ENABLE_SHL_R EQU 1      ; For Release versions
;ENABLE_SHL_D EQU 1      ; For Debug Versions
;ENABLE_SHL_T EQU 1      ; Verbose for Debug Versions
;ENABLE_SHL_STOP EQU 1   ; For Debug Versions


;------------------------------------------------------------------------
; Set HexLEDs - always, no pause - BE WARNED OF THE REGISTER ASSUMPTIONS!
;------------------------------------------------------------------------
    MACRO
    BL_SHL $ValueReg
        ldr     r0, =MAINSTONEII_BASE_REG_PA_FPGA
        str     $ValueReg,  [r0, #LEDDAT1_OFFSET]
    MEND

;------------------------------------------------------------------------
; Set HexLEDs - pause - BE WARNED OF THE REGISTER ASSUMPTIONS!
;------------------------------------------------------------------------
    MACRO
    BL_SHL_R $ValueReg, $pause

    IF :DEF: ENABLE_SHL_R
        BL_SHL $ValueReg
        BL_PAUSE $pause
    ELSE
        ; Intentionally empty
    ENDIF

    MEND
;------------------------------------------------------------------------
; Set HexLEDs - pause, debug - BE WARNED OF THE REGISTER ASSUMPTIONS!
;------------------------------------------------------------------------
    MACRO
    BL_SHL_D $ValueReg, $pause

    IF :DEF: ENABLE_SHL_D
        BL_SHL $ValueReg
        BL_PAUSE $pause
    ELSE
        ; Intentionally empty
    ENDIF

    MEND
;------------------------------------------------------------------------
; Set HexLEDs - pause, trace/verbose - BE WARNED OF THE REGISTER ASSUMPTIONS!
;------------------------------------------------------------------------
    MACRO
    BL_SHL_T $ValueReg, $pause

    IF :DEF: ENABLE_SHL_T
        BL_SHL $ValueReg
        BL_PAUSE $pause
    ELSE
        ; Intentionally empty
    ENDIF

    MEND

;------------------------------------------------------------------------
; Set HexLEDs - STOP - BE WARNED OF THE REGISTER ASSUMPTIONS!
;------------------------------------------------------------------------

    MACRO
    BL_SHL_STOP $ValueReg
    IF :DEF: ENABLE_SHL_STOP
        BL_SHL_D $ValueReg, 0xffffffff
    ELSE
        ; Intentionally empty
    ENDIF
    MEND

       
;------------------------------------------------------------------------
    
     
    ; Include memory configuration file with g_oalAddressTable
    ;
    INCLUDE oemaddrtab_cfg.inc
 
;-------------------------------------------------------------------------------
;
; OALStartUp: OEM OAL startup code.
;
; Inputs: None.
; 
; On return: N/A.
;
; Register used: r0
;
;-------------------------------------------------------------------------------
;
    ALIGN
    LEAF_ENTRY OALStartUp

    ldr   r1, =0xfff30000
    BL_SHL_T r1, BL_SHL_SHORTWAIT
    mov   r1, pc
    BL_SHL_T r1, BL_SHL_SHORTWAIT

ADDRESS_SAVE
    ; Save the address of this routine in the RESTART_DATA structure for use by GPIO RESET code in routine StartUp.
    ; The RESTART_DATA structure currently resides in SDRAM and the code below checks for that.
    ; If RESTART_DATA gets moved, GPIO reset will not work, but the platform should still boot.
    ; (This is intended to prevent boot failure if RESTART_DATA is not in writable memory.)

    ; check that the RESTART_DATA structure is in SDRAM
    ldr   r2, =RESTART_DATA_PA
    ldr   r1, =MAINSTONEII_BASE_PA_SDRAM
    cmp   r2, r1
    blo   ADDRESS_SAVE_ADDRESS_ERROR                ; save address < start of SDRAM
    ldr   r0, =RESTART_DATA_MAX_SIZE
    add   r2, r2, r0
    sub   r2, r2, #1                                ; end address of RESTART_DATA
    ldr   r0, =MAINSTONEII_SIZE_SDRAM
    add   r1, r1, r0
    sub   r1, r1, #1                                ; end address of SDRAM
    cmp   r2, r1
    bhs   ADDRESS_SAVE_ADDRESS_ERROR                ; end address of RESTART_DATA >= end of SDRAM
    
    ; Check the version of the RESTART_DATA structure
    ; If zero assume it hasn't been set and set it otherwise check that it matches what we expect
    ; The SDRAM SCRUB done by EBOOT clears all of SDRAM (including the RESTART_DATA structure)
    ldr   r0, =RESTART_DATA_PA
    ldr   r2, [r0, #RESTART_DATA_VERSION_OFFSET]    ; actual version
    ldr   r3, =RESTART_DATA_VERSION_VALUE           ; expected version
    cmp   r2, #0
    streq r3, [r0, #RESTART_DATA_VERSION_OFFSET]    ; actual version is zero - assume it hasn't been set
    moveq r2, r3
    cmp   r2, r3
    bne   ADDRESS_SAVE_VERSION_ERROR                ; version is not zero but is incorrect
    
    ; Save the entry point of this routine
    ldr   r0, =RESTART_DATA_PA
    add   r1, pc, #OALStartUp - (. + 8)             ; address of this routine
    str   r1, [r0, #RESTART_DATA_KERNEL_STARTUP_ADDRESS_OFFSET]
    
    BL_SHL_T r1, BL_SHL_SHORTWAIT                   ; address of this routine
    b     END_ADDRESS_SAVE
    
ADDRESS_SAVE_ADDRESS_ERROR
    ldr   r1, =0xfff300fd
    BL_SHL_R r2, BL_SHL_SHORTWAIT
    b     END_ADDRESS_SAVE

ADDRESS_SAVE_VERSION_ERROR
    ldr   r1, =0xfff300fe
    BL_SHL_R r1, BL_SHL_SHORTWAIT
    BL_SHL_R r2, BL_SHL_SHORTWAIT
    BL_SHL_R r3, BL_SHL_SHORTWAIT
    b     END_ADDRESS_SAVE

END_ADDRESS_SAVE
    ldr   r1, =0xfff300ff
    BL_SHL_T r1, BL_SHL_SHORTWAIT
    ldr   r1, =0xce050000
    BL_SHL_R r1, BL_SHL_NOWAIT
    
    ; Compute the OEMAddressTable's physical address and 
    ; load it into r0. KernelStart expects r0 to contain
    ; the physical address of this table. The MMU isn't 
    ; turned on until well into KernelStart.  
    ;
    add     r0, pc, #g_oalAddressTable - (. + 8)
    mov     r11, r0
    b       KernelStart
    nop
    nop
    nop
    nop
    nop
    nop
    
STALL
    b       STALL               ; Spin forever.


;-------------------------------------------------------------------------------
;
; Init_HexLEDs: Initializes the Mainstone II board logic to enable the hex LEDs.
;
; Inputs: None.
; 
; On return: N/A.
;
; Register used: r0-r3
;
;-------------------------------------------------------------------------------
;
    ALIGN
Init_HexLEDs

    ldr     r3, =BULVERDE_BASE_REG_PA_MEMC
    ldr     r2, =xlli_MSC1_value
    str     r2, [r3, #xlli_MSC1_offset]       ; Need to set MSC1 before trying to write to the HEX LEDs
    ldr     r2, [r3, #xlli_MSC1_offset]       ; Need to read it back to make sure the value latches (see MSC section of manual)

    ldr     r1, =MAINSTONEII_BASE_REG_PA_FPGA
    mov     r0, #0x0
    str     r0, [r1, #LEDCTL_OFFSET]          ; Blank hex & discrete leds
    setHexLED   r1, r0

  IF Interworking :LOR: Thumbing
    bx       lr
  ELSE
    mov      pc, lr                           ; Return to caller.
  ENDIF



;-------------------------------------------------------------------------------
;-------------------------------------------------------------------------------

    LTORG                           ; insert a literal pool here.

;
; TURN_ON_BTB - Enables the Branch Target Buffer
;
; Turn on the BTB via cp15.1[11] - Uses r0
;
;
    LEAF_ENTRY TURN_ON_BTB

    mcr p15, 0, r0, c7, c5, 0   ; flush the icache & BTB
    mrc p15, 0, r0, c1, c0, 0
    orr r0, r0, #0x800
    mcr p15, 0, r0, c1, c0, 0

  IF Interworking :LOR: Thumbing
    bx  lr
  ELSE
    mov  pc, lr          ; return
  ENDIF
   
        
    END 

;------------------------------------------------------------------------------