📄 dvm_dfm_api.c
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//
void VM_SetVoltage(DWORD DACValue)
{
unsigned char dataArray[3];
dataArray[0] = 0; //Command 0
dataArray[1] = (unsigned char)(DACValue & 0x000000FF);
dataArray[2] = (unsigned char)((DACValue & 0x0000FF00)>>8);
VM_MulitByte_Command(dataArray, 0, 3);
}
//***********************************************
//
// Bulverde B0 changes for the ComboChange()
// function.
// *TODO* wait for EOF
//***********************************************
/* **************************************************************************
* ComboChange: *TODO* This needs to be made into a platform-specific routine
*
* Inputs:
* LMult: This is the desired 'L' Value.
* NMult: This is the desired '2N' value.
* CPDIS: Set to disable the core PLL
* PPDIS: Set to disable the peripheral PLL. If CPDIS is cleared, this bit will be ignored.
* ABit: Set to invoke alternate setting for MEMC.
* PLL_EARLY: Set to pre-spin both PLLs. *Note: Can only do this when already in a 13M variant.
* LCD_26: Set to run LCDCLK = 26MHz while in 13M.
* turbo_mode_flag: Set if desired mode is Turbo Mode. *TODO* Range checking
* fastbus_mode_flag: Set if the desired System Bus mode is to be fast bus mode.
* DacValue: This is the value to be sent to the programmable voltage regulator via the PI2C interface. *TODO* LUT
*
* Description:
* Used to do all frequency changes. Based on current and destination operating points, we will either do a coupled VCS or a manual one.
* LMult and NMult will be ignored when CPDIS is set.
*
* Notice that if only setting Fast Bus Mode, we may require a manual voltage change. However, currently this is not possible
* based on the current operating points and voltages.
*
* The expectation is that at this time, all parameters must be defined to what the user actually wants.
*
* Cases where no VCS needs to happen:
* 1) New N, but not in Turbo mode
* 2) New A
* 3) ?new B? *TODO: handle this case
* 4) New PLL_EARLY (ensure only set when in 13M)
* 5) New LCD_26
*
* Cases where no FCS needs to happen:
* 1) PLL_EARLY (must already be in 13M)
*
*
* *TODO* -Add paramter validation including voltages: should i validate op-to-voltage?
* -Alter the DacValue parameter to be voltage and make a plat-specific LUT ~DONE~
* -Consider allowing NULL parameter to mean "leave as-is"... useful? ~ZBB~
* -For B1/C0: add 520MHz workaround
* -Ensure workaround is in place for PI2C bug (see linux patches)
* -Make param a struct ~DONE~
* -Add HT support
* **************************************************************************
*/
/* *****************************************************************************
* ValidParams: Validate input parameters to ComboChange.
*
* Error conditions:
* - CPDIS=1 && 'B'=1
* - Any non-POR frequency (build-time directive)
* ***************************************************************************** */
void fixupParams(COMBO_PARAM *cp, FREQ_VOLT_STATUS *fs)
{
//
// Fix up the current state members
//
cp->CPDIS &= 0x1;
cp->PPDIS &= 0x1;
cp->LCD_26 &= 0x1;
cp->PLL_EARLY &= 0x1;
cp->A_Bit &= 0x1;
cp->NMulti &= 0xF;
cp->LMulti &= 0x1F;
cp->fastbus_mode &= 0x1;
cp->turbo_mode &= 0x1;
cp->half_turbo_mode &= 0x1;
//
// Fix up the new state members
//
fs->CPDIS &= 0x1;
fs->PPDIS &= 0x1;
fs->LCD_26 &= 0x1;
fs->PLL_EARLY &= 0x1;
fs->A_Bit &= 0x1;
fs->NMulti &= 0xF;
fs->LMulti &= 0x1F;
fs->fastbus_mode &= 0x1;
fs->turbo_mode &= 0x1;
fs->half_turbo_mode &= 0x1;
}
BOOL ValidParameters(COMBO_PARAM *next, FREQ_VOLT_STATUS *current)
{
BOOL retval=TRUE;
//
// Core PLL on with peripheral PLL off is illegal
//
if (next->CPDIS==0 && next->PPDIS==1)
{
retval = FALSE;
}
//
// Cannot disable the core PLL while in fast bus mode
//
if (next->CPDIS==1 && next->fastbus_mode==1)
{
retval = FALSE;
}
//
// Check for PLL_EARLY if not already in 13M
// (Cannot do both at the same time; must set PLL_EARLY after
// entering 13M)
//
if (current->CPDIS==0 && next->PLL_EARLY==1)
{
retval = FALSE;
}
//
// Check for explicit clearing of PLL_EARLY (assume currently in 13M with it set).
// In this case, since this is so subtle, and does not really affect operation,
// we will just fix up on the behalf of the user:
// The PLL_EARLY bit will auto-clear after leaving 13M.
//
if((current->CPDIS && current->PLL_EARLY) && next->PLL_EARLY==0)
{
// Simply re-set PLL_EARLY in this case and return true.
//
next->PLL_EARLY=1;
}
//
// Only the Run or Run+Fast bus mode can be entered from 13M+ (i.e. not turbo nor normal 13M)
//
if((current->CPDIS==1 && current->PPDIS==0) && ((next->CPDIS==1 && next->PPDIS==1) || (next->turbo_mode==1)))
{
retval = FALSE;
}
//
// 13M+ mode can be entered only from normal run/fastbus mode and cannot be entered from normal 13M mode (i.e. not turbo nor normal 13M).
//
if((next->CPDIS==1 && next->PPDIS==0) && ((current->CPDIS==1 && current->PPDIS==1) || (current->turbo_mode==1)))
{
retval = FALSE;
}
//
// Validate L
//
if(FALSE==IsLValid(next, current))
{
retval = FALSE;
}
//
// Validate 2N
//
if(FALSE==Is2NValid(next, current))
{
retval = FALSE;
}
//
// Validate any fast bus wishes
//
if(FALSE==IsBValid(next, current))
{
retval = FALSE;
}
//
// Validate any HT mode wishes
//
if(FALSE==IsHTValid(next, current))
{
retval = FALSE;
}
return(retval);
}
// mem settings for L = 2-16, A = 1, B = 1
mem_cfg mem_cfg_A1B1[] =
{
{MSC0_26, DTC_26, DRI_26}, // 2
{MSC0_39, DTC_39, DRI_39}, // 3
{MSC0_52, DTC_52, DRI_52}, // 4
{MSC0_65, DTC_65, DRI_65}, // 5
{MSC0_78, DTC_78, DRI_78}, // 6
{MSC0_91, DTC_91, DRI_91}, // 7
{MSC0_104, DTC_104, DRI_104}, // 8
{MSC0_117, DTC_117, DRI_117}, // 9
{MSC0_130, DTC_130, DRI_130}, // 10
{MSC0_143, DTC_143, DRI_143}, // 11
{MSC0_156, DTC_156, DRI_156}, // 12
{MSC0_169, DTC_169, DRI_169}, // 13
{MSC0_182, DTC_182, DRI_182}, // 14
{MSC0_195, DTC_195, DRI_195}, // 15
{MSC0_208, DTC_208, DRI_208}, // 16
};
// mem settings for L = 2-31, A = 1, B = 0
mem_cfg mem_cfg_A1B0[] =
{
{MSC0_13, DTC_13, DRI_13}, // 2
{MSC0_19, DTC_19, DRI_19}, // 3
{MSC0_26, DTC_26, DRI_26}, // 4
{MSC0_32, DTC_32, DRI_32}, // 5
{MSC0_39, DTC_39, DRI_39}, // 6
{MSC0_45, DTC_45, DRI_45}, // 7
{MSC0_52, DTC_52, DRI_52}, // 8
{MSC0_58, DTC_58, DRI_58}, // 9
{MSC0_65, DTC_65, DRI_65}, // 10
{MSC0_71, DTC_71, DRI_71}, // 11
{MSC0_78, DTC_78, DRI_78}, // 12
{MSC0_84, DTC_84, DRI_84}, // 13
{MSC0_91, DTC_91, DRI_91}, // 14
{MSC0_97, DTC_97, DRI_97}, // 15
{MSC0_104, DTC_104, DRI_104}, // 16
{MSC0_110, DTC_110, DRI_110}, // 17
{MSC0_117, DTC_117, DRI_117}, // 18
{MSC0_124, DTC_124, DRI_124}, // 19
{MSC0_130, DTC_130, DRI_130}, // 20
{MSC0_136, DTC_136, DRI_136}, // 21
{MSC0_143, DTC_143, DRI_143}, // 22
{MSC0_149, DTC_149, DRI_149}, // 23
{MSC0_156, DTC_156, DRI_156}, // 24
{MSC0_162, DTC_162, DRI_162}, // 25
{MSC0_169, DTC_169, DRI_169}, // 26
{MSC0_175, DTC_175, DRI_175}, // 27
{MSC0_182, DTC_182, DRI_182}, // 28
{MSC0_188, DTC_188, DRI_188}, // 29
{MSC0_195, DTC_195, DRI_195}, // 30
{MSC0_201, DTC_201, DRI_201}, // 31
};
// mem settings for L = 2-31, A = 0, B = x
mem_cfg mem_cfg_A0Bx[] =
{
{MSC0_26, DTC_26, DRI_26}, // 2
{MSC0_39, DTC_39, DRI_39}, // 3
{MSC0_52, DTC_52, DRI_52}, // 4
{MSC0_65, DTC_65, DRI_65}, // 5
{MSC0_78, DTC_78, DRI_78}, // 6
{MSC0_91, DTC_91, DRI_91}, // 7
{MSC0_104, DTC_104, DRI_104}, // 8
{MSC0_117, DTC_117, DRI_117}, // 9
{MSC0_130, DTC_130, DRI_130}, // 10
{MSC0_71, DTC_71, DRI_71}, // 11
{MSC0_78, DTC_78, DRI_78}, // 12
{MSC0_84, DTC_84, DRI_84}, // 13
{MSC0_91, DTC_91, DRI_91}, // 14
{MSC0_97, DTC_97, DRI_97}, // 15
{MSC0_104, DTC_104, DRI_104}, // 16
{MSC0_110, DTC_110, DRI_110}, // 17
{MSC0_117, DTC_52, DRI_52}, // 18
{MSC0_124, DTC_52, DRI_52}, // 19
{MSC0_130, DTC_52, DRI_52}, // 20
{MSC0_68, DTC_52, DRI_52}, // 21
{MSC0_71, DTC_52, DRI_52}, // 22
{MSC0_74, DTC_52, DRI_52}, // 23
{MSC0_78, DTC_52, DRI_52}, // 24
{MSC0_81, DTC_81, DRI_81}, // 25
{MSC0_84, DTC_84, DRI_84}, // 26
{MSC0_87, DTC_87, DRI_87}, // 27
{MSC0_91, DTC_91, DRI_91}, // 28
{MSC0_94, DTC_94, DRI_94}, // 29
{MSC0_97, DTC_97, DRI_97}, // 30
{MSC0_100, DTC_100, DRI_100}, // 31
};
void mem_set_max(void)
{
XLLP_VUINT32_T t;
volatile XLLP_MEMORY_CONTROL_REGISTER_T *memc_reg = (volatile XLLP_MEMORY_CONTROL_REGISTER_T *)OALPAtoVA(BULVERDE_BASE_REG_PA_MEMC, FALSE);
memc_reg->MSC0 |= 0x7FF07FF0;
t = memc_reg->MSC0;
memc_reg->MSC1 |= 0x7FF07FF0;
t = memc_reg->MSC1;
memc_reg->MSC2 |= 0x7FF07FF0;
t = memc_reg->MSC2;
memc_reg->MDCNFG |= 0x03000300;
memc_reg->MDREFR = (memc_reg->MDREFR & (~MDREFR_DRI)) | 0x13;
}
// dfm function
void clock_set(int cccr, int clkcfg)
{
UINT32 MSC0;
UINT32 DTC;
UINT32 DRI;
UINT32 KxDBx;
int old_KxDBx;
int mdrefr;
int old_mdrefr;
mem_cfg *mem_tbl;
UINT32 L;
int tmp;
XLLP_FREQ_PARAM freq_status;
L = cccr & XLLP_CCCR_L;
// calculate KxDBx
KxDBx = calc_KxDBx(cccr & XLLP_CCCR_A, clkcfg & XLLP_CLKCFG_B, L);
// look up MSC0, DTC, DRI settings
if (cccr & XLLP_CCCR_A)
mem_tbl = (clkcfg & XLLP_CLKCFG_B)? mem_cfg_A1B1:mem_cfg_A1B0;
else
mem_tbl = mem_cfg_A0Bx;
MSC0 = mem_tbl[L - 2].MSC0;
DTC = mem_tbl[L - 2].DTC;
DRI = mem_tbl[L - 2].DRI;
old_mdrefr = memc_reg->MDREFR;
old_KxDBx = old_mdrefr & MDREFR_KxDBx;
mdrefr = (old_mdrefr & (~(MDREFR_KxDBx|MDREFR_DRI))) | KxDBx | DRI;
mem_set_max();
if (old_KxDBx != KxDBx)
{
if (old_KxDBx == MDREFR_K0DB2)
{
// if we are changing L from 8 to 16, set KxDBx first
// other wise sdram has trouble after DFM
memc_reg->MDREFR = (memc_reg->MDREFR & (~MDREFR_KxDBx)) | KxDBx;
tmp = memc_reg->MDREFR;
XllpXSC1FreqChange(clkcfg);
freq_status = XLLPGetCurrentFreqSetting(v_pClkReg);
// NKDbgPrintfW(TEXT("!!frequency %d\r\n"),freq_status.frequency);
// just read it for some let the cpu wati a little time
//XllpXSC1ReadCLKCFG();
memc_reg->MDREFR = mdrefr;
} else
{
// if we are changing L from 16 to 8,
// To set KxDBx first will cause SDRAM trouble
XllpXSC1FreqChange(clkcfg);
// just read it for some let the cpu wati a little time
//XllpXSC1ReadCLKCFG();
freq_status = XLLPGetCurrentFreqSetting(v_pClkReg);
//NKDbgPrintfW(TEXT("!!frequency %d\r\n"),freq_status.frequency);
memc_reg->MDREFR = mdrefr;
}
} else
{
XllpXSC1FreqChange(clkcfg);
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