mxc_i2s.c.bak

根据芯片WM8782在LINUX环境下实现的音频驱动

	ssi_dump();
#endif

	//mxc_clks_enable(SSI1_BAUD);
}

EXPORT_SYMBOL_GPL(mx27_i2s_slave_mode_config);


#if 0
void mx27_i2s_slave_mode_config(void)
{
	int ssi = SSI_CODEC;
//	printk("ssi=%d \n",ssi);
	ssi_enable(ssi,0); //disable ssi

	//interrupt config is in somewhere else.
	
//	ssi_synchronous_mode(ssi,1);// sync mode
	ssi_synchronous_mode(ssi,0);// async mode
	
//ssi_rx  
	ssi_rx_shift_direction(ssi,0); // MSB first shift
	ssi_rx_clock_polarity(ssi,1); // clock on rising edge
	ssi_rx_frame_sync_active(ssi,1);//sync low active
	ssi_rx_early_frame_sync(ssi,1); //init frame sync one bit before data is 
//received
	ssi_rx_frame_sync_length(ssi,1); //one bit length frame

	ssi_rx_word_length(ssi, ssi_16_bits);
	ssi_rx_frame_rate(ssi, 2); // two words per one frame 

	ssi_rx_clock_divide_by_two(ssi, 0);
	ssi_rx_clock_prescaler(ssi, 0);
	
	ssi_rx_fifo_full_watermark(ssi, ssi_fifo_0, RX_WATERMARK);
	ssi_rx_fifo_enable(ssi, ssi_fifo_0, 1);  //rx fifo0 enable
	
	ssi_receive_enable(ssi, 1);// receive section enable

	

	//ssi_rx_bit0(ssi, 1);

//ssi_tx
	ssi_tx_shift_direction(ssi,0); // MSB first shift
	ssi_tx_clock_polarity(ssi,1); // clock on falling edge
	ssi_tx_frame_sync_active(ssi,1); //sync low active
	ssi_tx_early_frame_sync(ssi,1);  //init frame sync one bit before data is 
//transmitted
	ssi_tx_frame_sync_length(ssi,1);
	
	ssi_tx_word_length(ssi, ssi_16_bits);
	ssi_tx_frame_rate(ssi, 2); // two words per one frame
       
        ssi_tx_clock_direction(ssi,0); // external bit clock 
        ssi_tx_frame_direction(ssi,0); // external frame sync
        
	ssi_tx_clock_divide_by_two(ssi, 0);
	ssi_tx_clock_prescaler(ssi, 0);

	ssi_tx_fifo_empty_watermark(ssi, ssi_fifo_0, TX_WATERMARK); 
	ssi_tx_fifo_enable(ssi, ssi_fifo_0, 1); // tx fifo0 enable

	ssi_transmit_enable(ssi, 1); // transmit section enable
	

	//ssi_tx_bit0(ssi, 1);

	ssi_enable(ssi,1);
	
	ssi_i2s_mode(ssi,2);
//	printk("SSI-%d enable the i2s slave mode\n",(SSI_CODEC + 1));

#if DBG	
	ssi_dump();
#endif

	//mxc_clks_enable(SSI1_BAUD);
}

EXPORT_SYMBOL_GPL(mx27_i2s_slave_mode_config);

 void mx27_i2s_normal_mode_config(void)
{
	int ssi = SSI_CODEC;
//	printk("normal ssi=%d \n",ssi);
	ssi_enable(ssi,0); //disable ssi

	//interrupt config is in somewhere else.
	
//	ssi_synchronous_mode(ssi,1);// sync mode
	ssi_synchronous_mode(ssi,0);// async mode
	ssi_network_mode(ssi,0); // Normal mode
	
//ssi_rx 
	ssi_rx_bit0(ssi, 1); 
	ssi_rx_shift_direction(ssi,0); // MSB first shift
	ssi_rx_clock_polarity(ssi,1); // clock on rising edge
	ssi_rx_frame_sync_active(ssi,0);//sync high active
	ssi_rx_early_frame_sync(ssi,0); // sync initiated as the first bit of data
	ssi_rx_frame_sync_length(ssi,0); //one word length frame

	ssi_rx_word_length(ssi, ssi_16_bits);
	ssi_rx_frame_rate(ssi, 2); // one words per one frame 

	ssi_rx_clock_divide_by_two(ssi, 0);
	ssi_rx_clock_prescaler(ssi, 0);
	
	ssi_rx_fifo_full_watermark(ssi, ssi_fifo_0, RX_WATERMARK);
	ssi_rx_fifo_enable(ssi, ssi_fifo_0, 1);  //rx fifo0 enable
	
	ssi_rx_mask_time_slot(ssi,0xFFFFFFFe); //unmask slot 0
	
	ssi_receive_enable(ssi, 1);// receive section enable

	



//ssi_tx
	ssi_tx_bit0(ssi, 1); 
	ssi_tx_shift_direction(ssi,0); // MSB first shift
	ssi_tx_clock_polarity(ssi,1); // clock on falling edge
	ssi_tx_frame_sync_active(ssi,0); //sync high active
	ssi_tx_early_frame_sync(ssi,0);  //sync initiated as the first bit of data
	ssi_tx_frame_sync_length(ssi,0); // one word length frame
	
	ssi_tx_word_length(ssi, ssi_16_bits);
	ssi_tx_frame_rate(ssi, 2); // one words per one frame
       
        ssi_tx_clock_direction(ssi,0); // external bit clock 
        ssi_tx_frame_direction(ssi,0); // external frame sync
        
	ssi_tx_clock_divide_by_two(ssi, 0);
	ssi_tx_clock_prescaler(ssi, 0);

	ssi_tx_fifo_empty_watermark(ssi, ssi_fifo_0, TX_WATERMARK); 
	ssi_tx_fifo_enable(ssi, ssi_fifo_0, 1); // tx fifo0 enable
	
	ssi_tx_mask_time_slot(ssi,0xFFFFFFFe); //unmask slot 0

	ssi_transmit_enable(ssi, 1); // transmit section enable
	


	ssi_enable(ssi,1);
	
	ssi_i2s_mode(ssi,0);
//	printk("SSI-%d enable the i2s slave mode\n",(SSI_CODEC + 1));

//for test ssi register value	
#if DBG
	ssi_dump();
#endif

	//mxc_clks_enable(SSI1_BAUD);
}
#endif 
#if 0
//gary modify 20080401
static void mx27_i2s_audmux_config(void)
{
	//ENTRY(0);
	unsigned long reg = 0;
	unsigned int addr = IO_ADDRESS(AUDMUX_BASE_ADDR);

	reg = (0<<31)| //Fs from the internal ssi1
	 	//(1<<30)| //clk to internal ssi1
	 	(0<<30)| //clk from the  internal ssi1
	 	//(4<<26)| //fs/clk <-->ignore
	 	(0<<25)| //ignored for sync mode
	   	(0<<24)|
	 	//(1<<24)|
	 	//(0<<20)|
	 	(4<<13)| //data <--> external ssi2
	 	(1<<12)| //sync
	 	(0<<10)|
	 	(0<<8)|
	 	(0<<0 );
	__raw_writel(reg, addr);//set the host port1(internal ssi1)

	//set the peripheral port2
	reg = (1<<31)| //Fs to the external ssi2
		//(0<<30)| //clk from the external ssi2
		(1<<30)| //clk from the internal ssi1
		(0<<26)| //fs/clk <-->internal ssi1
		(1<<25)| //ignored for sync mode
	   	(1<<24)|
	       //(0<<24)|
		(0<<20)| 
		(0<<13)| //data <-->internal ssi1, 0 means internal ssi1, 
		(1<<12)|  //sync
		(0<<10);
	__raw_writel(reg, addr+0x14);//set the port5(external ssi2)		

}
//gary modify 20080401 end
#endif

static void mx27_i2s_audmux_config(void)
{
	//ENTRY(0);
	unsigned long reg = 0;
	unsigned int addr = IO_ADDRESS(AUDMUX_BASE_ADDR);

	reg = 
		//(0<<31)| //Fs from the internal ssi1
	 	(1<<31)| //clk to internal ssi1
	 	(1<<30)| //clk from the  internal ssi1
	 	(4<<26)| 
	 	(1<<25)| //ignored for sync mode
	   	(1<<24)|
	 	(4<<20)|
	 	(4<<13)| //data <--> external ssi2
	 	(1<<12)| //sync
	 	(0<<10)|
	 	(0<<8)|
	 	(0<<0 );
	__raw_writel(reg, addr);//set the host port1(internal ssi1)

	//set the peripheral port2
	reg = (0<<31)| //Fs to the external ssi2
		//(0<<30)| //clk from the external ssi2
		(0<<30)| //clk from the internal ssi1
		(0<<26)| //fs/clk <-->internal ssi1
		(0<<25)| //ignored for sync mode
	   	(0<<24)|
		(0<<20)| 
		(0<<13)| //data <-->internal ssi1, 0 means internal ssi1, 
		(1<<12)|  //sync
		(0<<10);
	__raw_writel(reg, addr+0x14);//set the port5(external ssi2)		
}



static struct clk *ssi_clk_0;//* ssi_clk_1;
static int __init mxc_i2s_init(void)
{	

//	gpio_ssi_active(SSI1);//external ssi1(4 port)
	gpio_ssi_active(SSI2);//external ssi2-port(5 port)
//	gpio_ssi_active(SSI3); //external ssi3 port(6 port)
	//mxc_clks_enable(SSI1_BAUD);
	//07-11-2007
	ssi_clk_0= clk_get(NULL, "ssi_clk.0");
	clk_enable(ssi_clk_0);
	//clk_put(ssi_clk_0);
//	ssi_clk_1 = clk_get(NULL, "ssi_clk.1");
//	clk_enable(ssi_clk_1);
	//clk_put(ssi_clk_1);
	
	mx27_i2s_slave_mode_config();
//	mx27_i2s_master_mode_config();
	mx27_i2s_audmux_config(); 
	printk(KERN_INFO "SSI-I2S conf & ops loaded\n");
	return 0;
}


static void __exit mxc_i2s_exit(void)
{
//    gpio_ssi_inactive(SSI1);// external ssi1(4 port)
	gpio_ssi_inactive(SSI2);//external ssi2-port(5 port)
//	gpio_ssi_inactive(SSI3); //external ssi3 port(6 port)
	//mxc_clks_disable(SSI1_BAUD);
	clk_disable(ssi_clk_0);
	clk_put(ssi_clk_0);
//	clk_disable(ssi_clk_1);
//	clk_put(ssi_clk_1);
	
	ssi_enable(SSI_CODEC,0);
	printk(KERN_INFO "SSI-I2S conf & ops unloaded\n");
}



module_init(mxc_i2s_init);
module_exit(mxc_i2s_exit);

MODULE_DESCRIPTION("mxc i2s driver");
MODULE_LICENSE("GPL");