mxc_i2s.c.bak

根据芯片WM8782在LINUX环境下实现的音频驱动

/* ========================================================================== */
/*                                                                            */
/*   Filename.c                                                               */
/*   (c) 2001 Author                                                          */
/*                                                                            */
/*   Description                                                              */
/*                                                                            */
/* ========================================================================== */

/*
 *  Copyright (c) sitek hengke elec .Ltd <ihanker.com>
 *
 *   This program is free software; you can redistribute it and/or modify
 *   it under the terms of the GNU General Public License as published by
 *   the Free Software Foundation; either version 2 of the License, or
 *   (at your option) any later version.
 */

#include <asm/io.h>
#include <asm/delay.h>

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/clk.h>

#include <asm/arch/clock.h>
#include "ssi.h"
#include "registers.h"

extern void gpio_ssi_active(int);
extern void gpio_ssi_inactive(int);

#define SSI_CODEC SSI1//0
//#define SSI_CODEC SSI2  // 1 
//zd modify
//Julian, NOTE: use SSI1 directly somewhere.

#define TX_WATERMARK	0x4   //set tx_fifo watermark
#define RX_WATERMARK	0x6  // set rx_fifo watermark

//#define SSI3 2

#define  DBG 0

//static int sisr_reg = IO_ADDRESS(SSI1_BASE_ADDR)+MXC_SSISISR;


#if DBG
static int getreg_value(unsigned int offset ,int ssi)
{
	volatile unsigned long reg = 0;
	unsigned int base_addr = 0;
	
	base_addr = (ssi == SSI1) ? IO_ADDRESS(SSI1_BASE_ADDR) :IO_ADDRESS(SSI2_BASE_ADDR);
	reg = __raw_readl(base_addr + offset);
	
	return reg;
	
}

static void ssi_dump(void)
{
	//ENTRY(0);
	int reg=0;
	
	reg = getreg_value(MXC_SSISTX0,0);
	printk("MXC_SSISTX0=0x%x\n",reg);
	
	reg = getreg_value(MXC_SSISTX1,0);
	printk("MXC_SSISTX1=0x%x\n",reg);
	
	reg = getreg_value(MXC_SSISRX0,0);
	printk("MXC_SSISRX0=0x%x\n",reg);
	
	reg = getreg_value(MXC_SSISRX1,0);
	printk("MXC_SSISRX1=0x%x\n",reg);
	
	reg = getreg_value(MXC_SSISCR,0);
	printk("MXC_SSISCR=0x%x\n",reg);
	
	reg = getreg_value(MXC_SSISISR,0);
	printk("MXC_SSISISR=0x%x\n",reg);
	
	reg = getreg_value(MXC_SSISIER,0);
	printk("MXC_SSISIER=0x%x\n",reg);
	
	reg = getreg_value(MXC_SSISTCR,0);
	printk("MXC_SSISTCR=0x%x\n",reg);
	
	reg = getreg_value(MXC_SSISRCR,0);
	printk("MXC_SSISRCR=0x%x\n",reg);
	
	reg = getreg_value(MXC_SSISTCCR,0);
	printk("MXC_SSISTCCR=0x%x\n",reg);
	
	reg = getreg_value(MXC_SSISRCCR,0);
	printk("MXC_SSISRCCR=0x%x\n",reg);
	
	reg = getreg_value(MXC_SSISFCSR,0);
	printk("MXC_SSISFCSR=0x%x\n",reg);
	
	reg = getreg_value(MXC_SSISTR,0);
	printk("MXC_SSISTR=0x%x\n",reg);
	
	reg = getreg_value(MXC_SSISOR,0);
	printk("MXC_SSISOR=0x%x\n",reg);
	
	reg = getreg_value(MXC_SSISACNT,0);
	printk("MXC_SSISACNT=0x%x\n",reg);
	
	reg = getreg_value(MXC_SSISACADD,0);
	printk("MXC_SSISACADD=0x%x\n",reg);
	
	reg = getreg_value(MXC_SSISACDAT,0);
	printk("MXC_SSISACDAT=0x%x\n",reg);
	
	reg = getreg_value(MXC_SSISATAG,0);
	printk("MXC_SSISATAG=0x%x\n",reg);
	
	reg = getreg_value(MXC_SSISTMSK,0);
	printk("MXC_SSISTMSK=0x%x\n",reg);
	
	reg = getreg_value(MXC_SSISRMSK,0);
	printk("MXC_SSISRMSK=0x%x\n",reg);
}
#endif

//EXPORT_SYMBOL_GPL(ssi_dump);
#if 0
void mx27_i2s_master_mode_config(void)
{
	//ENTRY(0);
	int ssi = SSI_CODEC;
	printk("ssi=%d \n",ssi);
	ssi_enable(ssi,0); //disable ssi

	//interrupt config is in somewhere else.
	
	ssi_synchronous_mode(ssi,1);// sync mode
//	ssi_synchronous_mode(ssi,0);// async mode

	ssi_system_clock(ssi,1);//enable system clock: zd
	ssi_two_channel_mode(ssi, 1); // two channel enabel zd
//ssi_rx  
	ssi_rx_shift_direction(ssi,0); // MSB first shift
	ssi_rx_clock_polarity(ssi,1); // clock on rising edge
	ssi_rx_frame_sync_active(ssi,1);//sync low active
	ssi_rx_early_frame_sync(ssi,1); //init frame sync one bit before data is received

//done by hardware automatically
	//ssi_network_mode(ssi, 1); // network mode is selectd
	ssi_rx_frame_sync_length(ssi,0); //one bit length frame
	ssi_rx_bit0(ssi, 1); // shifting w.r.t. bit 0 of RXSR

//received
	//ssi_rx_word_length(ssi, ssi_16_bits);
	//ssi_rx_frame_rate(ssi, 2); // two words per one frame 

	//ssi_rx_clock_divide_by_two(ssi, 0);
	//ssi_rx_clock_prescaler(ssi, 0);
	
	ssi_rx_fifo_full_watermark(ssi, ssi_fifo_0, RX_WATERMARK);
	ssi_rx_fifo_enable(ssi, ssi_fifo_0, 1);  //rx fifo0 enable
	
	ssi_receive_enable(ssi, 1);// receive section enable



//ssi_tx
	ssi_tx_shift_direction(ssi,0); // MSB first shift
	ssi_tx_clock_polarity(ssi,1); // clock on falling edge
	ssi_tx_frame_sync_active(ssi,1); //sync low active
	ssi_tx_early_frame_sync(ssi,1);  //init frame sync one bit before data is 

//done by hardware automatically
	ssi_network_mode(ssi, 1); // network mode is selectd
	ssi_tx_frame_sync_length(ssi,0); //one bit length frame
	ssi_tx_bit0(ssi, 1); // shifting w.r.t. bit 0 of RXSR

//transmitted
 	 ssi_tx_clock_direction(ssi,1); // internal bit clock 
        ssi_tx_frame_direction(ssi,1); // internal frame sync
        	
	ssi_tx_word_length(ssi, ssi_16_bits);
    //ssi_tx_frame_rate(ssi, 2); // two words per one frame 
       ssi_tx_frame_rate(ssi, 8); //  2 words per one frame,modify by zd
       ssi_tx_prescaler_modulus(ssi, 16);
	   	
	//ssi_tx_clock_divide_by_two(ssi, 0);
	ssi_tx_clock_prescaler(ssi, 0); //modify by zd
	//ssi_tx_clock_prescaler(ssi, 0);
	ssi_tx_clock_divide_by_two(ssi, 0);
	

	ssi_tx_fifo_empty_watermark(ssi, ssi_fifo_0, TX_WATERMARK); 
	ssi_tx_fifo_enable(ssi, ssi_fifo_0, 1); // tx fifo0 enable

	ssi_transmit_enable(ssi, 1); // transmit section enable
	
	
	ssi_enable(ssi,1);
	
	ssi_i2s_mode(ssi,1);
//	printk("SSI-%d enable the i2s slave mode\n",(SSI_CODEC + 1));

#if DBG	
	ssi_dump();
#endif

	//mxc_clks_enable(SSI1_BAUD);
}

EXPORT_SYMBOL_GPL(mx27_i2s_master_mode_config);
#endif


void mx27_i2s_slave_mode_config(void)
{
	int ssi = SSI_CODEC;
//	printk("ssi=%d \n",ssi);
	ssi_enable(ssi,0); //disable ssi

	//interrupt config is in somewhere else.
	
	ssi_synchronous_mode(ssi,1);// sync mode
//	ssi_synchronous_mode(ssi,0);// async mode
	
//ssi_rx  
	ssi_rx_shift_direction(ssi,0); // MSB first shift
	ssi_rx_clock_polarity(ssi,1); // clock on rising edge
	ssi_rx_frame_sync_active(ssi,1);//sync low active
	ssi_rx_early_frame_sync(ssi,1); //init frame sync one bit before data is 
//received
//done by hardware auto
	ssi_network_mode(ssi, 0);
	ssi_rx_frame_sync_length(ssi,1); //one bit length frame
	ssi_rx_bit0(ssi, 1); // shifting w.r.t. bit 0 of TXSR
	
	ssi_rx_word_length(ssi, ssi_16_bits);
	ssi_rx_frame_rate(ssi, 2); // two words per one frame 

	ssi_rx_clock_divide_by_two(ssi, 0);
	ssi_rx_clock_prescaler(ssi, 0);
	
	ssi_rx_fifo_full_watermark(ssi, ssi_fifo_0, RX_WATERMARK);
	ssi_rx_fifo_enable(ssi, ssi_fifo_0, 1);  //rx fifo0 enable
	
	ssi_receive_enable(ssi, 1);// receive section enable

	

	//ssi_rx_bit0(ssi, 1);

//ssi_tx
	ssi_tx_shift_direction(ssi,0); // MSB first shift
	ssi_tx_clock_polarity(ssi,1); // clock on falling edge
	ssi_tx_frame_sync_active(ssi,1); //sync low active
	ssi_tx_early_frame_sync(ssi,1);  //init frame sync one bit before data is 
//transmitted
	ssi_tx_frame_sync_length(ssi,1);
	ssi_tx_bit0(ssi, 1); // shifting w.r.t. bit 0 of RXSR
	
	ssi_tx_word_length(ssi, ssi_16_bits);
	ssi_tx_frame_rate(ssi, 2); // two words per one frame
       
        ssi_tx_clock_direction(ssi,0); // external bit clock 
        ssi_tx_frame_direction(ssi,0); // external frame sync
        
	ssi_tx_clock_divide_by_two(ssi, 0);
	ssi_tx_clock_prescaler(ssi, 0);

	ssi_tx_fifo_empty_watermark(ssi, ssi_fifo_0, TX_WATERMARK); 
	ssi_tx_fifo_enable(ssi, ssi_fifo_0, 1); // tx fifo0 enable

	ssi_transmit_enable(ssi, 1); // transmit section enable
	

	//ssi_tx_bit0(ssi, 1);

	ssi_enable(ssi,1);
	
	ssi_i2s_mode(ssi,2);
//	printk("SSI-%d enable the i2s slave mode\n",(SSI_CODEC + 1));

#if DBG