s1d13806.h~

linux下的VIDEO接口驱动程序

//----------------------------------------------------------------------------
//
//  File generated by S1D13806CFG.EXE
//
//  Copyright (c) 2000,2001 Epson Research and Development, Inc.
//  All rights reserved.
//
//  PLEASE NOTE: If you FTP this file to a non-Windows platform, make
//               sure you transfer this file using ASCII, not BINARY mode.
//
//----------------------------------------------------------------------------

// CRT:    (active)   640x480 60Hz (PCLK=CLKI=25.175MHz)
// Memory: Embedded SDRAM (MCLK=CLKI3=50.000MHz) (BUSCLK=60.000MHz)


//#define S1D_DISPLAY_WIDTH           640
//#define S1D_DISPLAY_HEIGHT          480

#define S1D_DISPLAY_WIDTH           800
#define S1D_DISPLAY_HEIGHT          480

#define S1D_DISPLAY_BPP             16
//#define S1D_DISPLAY_SCANLINE_BYTES  1280
#define S1D_DISPLAY_SCANLINE_BYTES  1600
#define S1D_PHYSICAL_VMEM_ADDR      0x30200000L



//#define S1D_PHYSICAL_VMEM_SIZE      0x140000L
#define S1D_PHYSICAL_VMEM_SIZE      0x160000L
#define S1D_PHYSICAL_REG_ADDR       0x30000000L
#define S1D_PHYSICAL_REG_SIZE       0x200
//#define S1D_DISPLAY_PCLK            25175
#define S1D_DISPLAY_PCLK            33330
#define S1D_PALETTE_SIZE            65535
//#define S1D_PALETTE_SIZE            256
#define S1D_FRAME_RATE              60
#define S1D_POWER_DELAY_ON          0
#define S1D_POWER_DELAY_OFF         120
#define S1D_CRT
#define S1D_HWBLT
#define S1D_HW_CURSOR
#define S1D_REGDELAYOFF             0xFFFE
#define S1D_REGDELAYON              0xFFFF

#define S1D_WRITE_PALETTE(p,i,r,g,b)  \
{  \
    ((volatile S1D_VALUE*)(p))[0x1E2/sizeof(S1D_VALUE)] = (S1D_VALUE)(i);  \
    ((volatile S1D_VALUE*)(p))[0x1E4/sizeof(S1D_VALUE)] = (S1D_VALUE)(r);  \
    ((volatile S1D_VALUE*)(p))[0x1E4/sizeof(S1D_VALUE)] = (S1D_VALUE)(g);  \
    ((volatile S1D_VALUE*)(p))[0x1E4/sizeof(S1D_VALUE)] = (S1D_VALUE)(b);  \
}

#define S1D_READ_PALETTE(p,i,r,g,b)  \
{  \
    ((volatile S1D_VALUE*)(p))[0x1E2/sizeof(S1D_VALUE)] = (S1D_VALUE)(i);  \
    r = ((volatile S1D_VALUE*)(p))[0x1E4/sizeof(S1D_VALUE)];  \
    g = ((volatile S1D_VALUE*)(p))[0x1E4/sizeof(S1D_VALUE)];  \
    b = ((volatile S1D_VALUE*)(p))[0x1E4/sizeof(S1D_VALUE)];  \
}

typedef unsigned short S1D_INDEX;
typedef unsigned char  S1D_VALUE;

typedef struct
{
    S1D_INDEX Index;
    S1D_VALUE Value;
} S1D_REGS;






static S1D_REGS aS1DRegs[] = 
{
    {0x0001,0x00},   // Miscellaneous Register  
    {0x01FC,0x00},   // Display Mode Register
    {0x0004,0x00},   // General IO Pins Configuration Register 0
    {0x0004,0x00},	//{0x0005,0x08},   // General IO Pins Configuration Register 1        
    {0x0008,0x00},   // General IO Pins Control Register 0
    {0x0008,0x00},	//{0x0009,0x00},   // General IO Pins Control Register  
    {0x0010,0x01},   // Memory Clock Configuration Register
    {0x0014,0x00},   // LCD Pixel Clock Configuration Register
    {0x0018,0x00},   // CRT/TV Pixel Clock Configuration Register
    {0x001C,0x00},   // MediaPlug Clock Configuration Register
    //{0x001C,0x01},   // MediaPlug Clock Configuration Register    
    {0x001E,0x02},   // CPU To Memory Wait State Select Register
    //{0x001E,0x01},   // CPU To Memory Wait State Select Register    
    {0x0020,0x00},   // Memory Configuration Register 
    //{0x0020,0x80},   // Memory Configuration Register   
    {0x0021,0x05},   // DRAM Refresh Rate Register
    //{0x0021,0x03},   // DRAM Refresh Rate Register   
    {0x002A,0x12},   // DRAM Timings Control Register 0
    //{0x002A,0x00},   // DRAM Timings Control Register 0  
    {0x002B,0x02},   // DRAM Timings Control Register 1
    //{0x002B,0x01},   // DRAM Timings Control Register 1     
    {0x0030,0x25},   // Panel Type Register
    {0x0031,0x00},   // MOD Rate Register   
    {0x0032,0x63},   // LCD Horizontal Display Width Register
//    {0x0032,0x4f},   // LCD Horizontal Display Width Register 
    {0x0034,0x12},   // LCD Horizontal Non-Display Period Register
    {0x0035,0x01},   // TFT FPLINE Start Position Register
    {0x0036,0x0B},   // TFT FPLINE Pulse Width Register
    {0x0038,0xDF},   // LCD Vertical Display Height Register 0
    {0x0039,0x01},   // LCD Vertical Display Height Register 1
    {0x003A,0x2C},   // LCD Vertical Non-Display Period Register 
    {0x003B,0x0b},   // TFT FPFRAME Start Position Register
//    {0x003B,0x0a},   // TFT FPFRAME Start Position Register   
    {0x003C,0x01},   // TFT FPFRAME Pulse Width Register
    {0x0040,0x05},   // LCD Display Mode Register
    {0x0041,0x01},   // LCD Miscellaneous Register
    //{0x0041,0x00},   // LCD Miscellaneous Register    
    {0x0042,0x00},   // LCD Display Start Address Register 0
    {0x0043,0x00},   // LCD Display Start Address Register 1
    {0x0044,0x00},   // LCD Display Start Address Register 
    {0x0046,0x20},   // LCD Memory Address Offset Register 0
 //   {0x0046,0x80},   // LCD Memory Address Offset Register 0    
    {0x0047,0x03},   // LCD Memory Address Offset Register 1
 //   {0x0047,0x02},   // LCD Memory Address Offset Register 1    
    {0x0048,0x00},   // LCD Pixel Panning Register
    {0x004A,0x00},   // LCD Display FIFO High Threshold Control Register
    {0x004B,0x00},   // LCD Display FIFO Low Threshold Control Register
    {0x0050,0x4F},   // CRT/TV Horizontal Display Width Register
    {0x0052,0x13},   // CRT/TV Horizontal Non-Display Period Register
    {0x0053,0x01},   // CRT/TV HRTC Start Position Register
    {0x0054,0x0B},   // CRT/TV HRTC Pulse Width Register
    {0x0056,0xDF},   // CRT/TV Vertical Display Height Register 0
    {0x0057,0x01},   // CRT/TV Vertical Display Height Register 1
    {0x0058,0x2B},   // CRT/TV Vertical Non-Display Period Register
    {0x0059,0x09},   // CRT/TV VRTC Start Position Register
    {0x005A,0x01},   // CRT/TV VRTC Pulse Width Register
    {0x005B,0x08},   // TV Output Control Register
  //   {0x005B,0x10},   // TV Output Control Register 
    {0x0060,0x05},   // CRT/TV Display Mode Register
    {0x0062,0x00},   // CRT/TV Display Start Address Register 0
    {0x0063,0x00},   // CRT/TV Display Start Address Register 1
    {0x0064,0x00},   // CRT/TV Display Start Address Register 2
    {0x0066,0x80},   // CRT/TV Memory Address Offset Register 0
    {0x0067,0x02},   // CRT/TV Memory Address Offset Register 1
    {0x0068,0x00},   // CRT/TV Pixel Panning Register
    {0x006A,0x00},   // CRT/TV Display FIFO High Threshold Control Register
    {0x006B,0x00},   // CRT/TV Display FIFO Low Threshold Control Register
    {0x0070,0x00},   // LCD Ink/Cursor Control Register
    {0x0071,0x01},   // LCD Ink/Cursor Start Address Register
    {0x0072,0x00},   // LCD Cursor X Position Register 0
    {0x0073,0x00},   // LCD Cursor X Position Register 1
    {0x0074,0x00},   // LCD Cursor Y Position Register 0
    {0x0075,0x00},   // LCD Cursor Y Position Register 1
    {0x0076,0x00},   // LCD Ink/Cursor Blue Color 0 Register
    {0x0077,0x00},   // LCD Ink/Cursor Green Color 0 Register
    {0x0078,0x00},   // LCD Ink/Cursor Red Color 0 Register
    {0x007A,0x1F},   // LCD Ink/Cursor Blue Color 1 Register
    {0x007B,0x3F},   // LCD Ink/Cursor Green Color 1 Register
    {0x007C,0x1F},   // LCD Ink/Cursor Red Color 1 Register
    {0x007E,0x00},   // LCD Ink/Cursor FIFO Threshold Register