init.c

linux下的VIDEO接口驱动程序

   SiS_UnLockCRT2(HwDeviceExtension, BaseAddr);
   SiS_SetReg1(SiS_Part1Port,0x00,0x00);
   SiS_SetReg1(SiS_Part1Port,0x02,*pSiS_CRT2Data_1_2);

#ifdef SIS315H                            /* 05/02/01 ynlai  for sis550 */
   if((HwDeviceExtension->jChipType == SIS_315H) ||
      (HwDeviceExtension->jChipType == SIS_315PRO) ||
      (HwDeviceExtension->jChipType == SIS_550)||
      (HwDeviceExtension->jChipType == SIS_640)||   /* 08/20/01 chiawen for 640/740 */
      (HwDeviceExtension->jChipType == SIS_740)||   /* 09/03/01 chiawen for 640/740 */
      (HwDeviceExtension->jChipType == SIS_650))    /* 09/03/01 chiawen for 650 */
     	SiS_SetReg1(SiS_Part1Port,0x2E,0x08); /* use VB */
#endif

   temp=*pSiS_SR32;
   if(!SiS_BridgeIsOn(BaseAddr)) {
     	temp=temp&0xEF;
   }
   SiS_SetReg1(SiS_P3c4,0x32,temp);

#ifdef SIS315H
   if ((HwDeviceExtension->jChipType == SIS_315H) ||
       (HwDeviceExtension->jChipType == SIS_315PRO)) {
     HwDeviceExtension->pQueryVGAConfigSpace(HwDeviceExtension,0x50,0,&Temp);  /* Get */
     Temp >>= 20;
     Temp &= 0xF;
     if (Temp!=1) {
     	SiS_SetReg1(SiS_P3c4,0x25,SiS_SR25[1]);
     	SiS_SetReg1(SiS_P3d4,0x49,SiS_CR49[1]);
     }

     SiS_SetReg1(SiS_P3c4,0x27,0x1F);

     SiS_SetReg1(SiS_P3c4,0x31,*pSiS_SR31);
     SiS_SetReg1(SiS_P3c4,0x32,*pSiS_SR32);
     SiS_SetReg1(SiS_P3c4,0x33,*pSiS_SR33);
   }
#endif

   if (SiS_BridgeIsOn(BaseAddr)==1) {
     	if(SiS_IF_DEF_LVDS==0) {
       		SiS_SetReg1(SiS_Part2Port,0x00,0x1C);
       		SiS_SetReg1(SiS_Part4Port,0x0D,*pSiS_CRT2Data_4_D);
       		SiS_SetReg1(SiS_Part4Port,0x0E,*pSiS_CRT2Data_4_E);
       		SiS_SetReg1(SiS_Part4Port,0x10,*pSiS_CRT2Data_4_10);
       		SiS_SetReg1(SiS_Part4Port,0x0F,0x3F);
     	}
     	SiS_LockCRT2(HwDeviceExtension, BaseAddr);
   }
   SiS_SetReg1(SiS_P3d4,0x83,0x00);
/*   SetDefExt1Regs end */

#ifdef SIS315H
   if ((HwDeviceExtension->jChipType==SIS_315H)||
       (HwDeviceExtension->jChipType==SIS_315PRO)) { /* 05/02/01 ynlai */
       	if (HwDeviceExtension->bSkipDramSizing==TRUE) {
         	SiS_SetDRAMModeRegister(ROMAddr);
         	pSR = HwDeviceExtension->pSR;
         	if (pSR!=NULL) {
           		while (pSR->jIdx!=0xFF) {
             			SiS_SetReg1(SiS_P3c4,pSR->jIdx,pSR->jVal);
             			pSR++;
           		}
         	}
       } else SiS_SetDRAMSize_310(HwDeviceExtension);
   }
#endif

#ifdef SIS315H
   if((HwDeviceExtension->jChipType==SIS_550)){ /* 05/02/01 ynlai For SiS 550 */
       /* SetDRAMConfig begin */
/*     SiS_SetReg1(SiS_P3c4,0x12,SR12);
       SiS_SetReg1(SiS_P3c4,0x13,SR13);
       SiS_SetReg1(SiS_P3c4,0x14,SR14);
       SiS_SetReg1(SiS_P3c4,0x16,SR16);
       SiS_SetReg1(SiS_P3c4,0x17,SR17);
       SiS_SetReg1(SiS_P3c4,0x18,SR18);
       SiS_SetReg1(SiS_P3c4,0x19,SR19);
       SiS_SetReg1(SiS_P3c4,0x1A,SR1A);   */
       /* SetDRAMConfig end */
   }
#endif

#ifdef SIS300
   if( HwDeviceExtension->jChipType==SIS_300) {       /* For SiS 300 Chip  */
       	if (HwDeviceExtension->bSkipDramSizing==TRUE) {
/*       	SiS_SetDRAMModeRegister(ROMAddr);
         	temp = (HwDeviceExtension->pSR)->jVal;
         	SiS_SetReg1(SiS_P3c4,0x13,temp);
         	temp = (HwDeviceExtension->pSR)->jVal;
         	SiS_SetReg1(SiS_P3c4,0x14,temp);   */
       } else {
#ifdef TC
         	SiS_SetReg1(SiS_P3c4,0x13,SR13);
         	SiS_SetReg1(SiS_P3c4,0x14,SR14);
         	SiS_SetRegANDOR(SiS_P3c4,0x15,0xFF,0x04);
#else
         	SiS_SetDRAMSize_300(HwDeviceExtension);
         	SiS_SetDRAMSize_300(HwDeviceExtension);
#endif
       }
   }
   if((HwDeviceExtension->jChipType==SIS_540)||       /* For SiS 630/540/730 Chip  */
      (HwDeviceExtension->jChipType==SIS_630)||
      (HwDeviceExtension->jChipType==SIS_730)){
       	/* SetDRAMConfig begin */
#if 0
     	SiS_SetReg1(SiS_P3c4,0x12,SR12);
       	SiS_SetReg1(SiS_P3c4,0x13,SR13);
       	SiS_SetReg1(SiS_P3c4,0x14,SR14);
       	SiS_SetReg1(SiS_P3c4,0x16,SR16);
       	SiS_SetReg1(SiS_P3c4,0x17,SR17);
       	SiS_SetReg1(SiS_P3c4,0x18,SR18);
       	SiS_SetReg1(SiS_P3c4,0x19,SR19);
       	SiS_SetReg1(SiS_P3c4,0x1A,SR1A);
#endif
       	/* SetDRAMConfig end */
   }
/* SetDRAMSize end */
#endif /* SIS300 */

/*   SetDefExt2Regs begin  */
#if 0
   AGP=1;
   temp=(UCHAR)SiS_GetReg1(SiS_P3c4,0x3A);
   temp=temp&0x30;
   if(temp==0x30) AGP=0;
   if(AGP==0) *pSiS_SR21=*pSiS_SR21&0xEF;
   SiS_SetReg1(SiS_P3c4,0x21,*pSiS_SR21);
   if(AGP==1) *pSiS_SR22=*pSiS_SR22&0x20;
   SiS_SetReg1(SiS_P3c4,0x22,*pSiS_SR22);
#endif
   SiS_SetReg1(SiS_P3c4,0x21,*pSiS_SR21);
   SiS_SetReg1(SiS_P3c4,0x22,*pSiS_SR22);
/*   SetDefExt2Regs end  */

#if 0
   SiS_SetReg3(SiS_P3c6,0xff);
   SiS_ClearDAC(SiS_P3c8);        /* [ynlai] 05/22/01 */
#endif

   SiS_DetectMonitor(HwDeviceExtension,BaseAddr);
   SiS_GetSenseStatus(HwDeviceExtension,ROMAddr);      /* sense CRT2 */

   return(TRUE);
}

void
SiS_Set_LVDS_TRUMPION(PSIS_HW_DEVICE_INFO HwDeviceExtension)
{
  USHORT temp=0;

#ifdef SiS300
  if ((HwDeviceExtension->jChipType == SIS_540)||
      (HwDeviceExtension->jChipType == SIS_630)||
      (HwDeviceExtension->jChipType == SIS_730)) {
        /* TW: Read POWER_ON_TRAP and copy to CR37 */
    	temp = (UCHAR)SiS_GetReg1(SiS_P3c4,0x1A);
    	temp=(temp&0xE0)>>4;
   	SiS_SetRegANDOR(SiS_P3d4,0x37,0xF1,temp);
   }
#endif

   /* Set globals SiS_IF_DEF... */
   SiSSetLVDSetc(HwDeviceExtension, 0);
}

/* ===============  for 300 dram sizing begin  =============== */
#ifdef SIS300
void
SiS_SetDRAMSize_300(PSIS_HW_DEVICE_INFO HwDeviceExtension)
{
   /*ULONG   ROMAddr  = (ULONG)HwDeviceExtension->pjVirtualRomBase;*/
   ULONG   FBAddr   = (ULONG)HwDeviceExtension->pjVideoMemoryAddress;
   /*USHORT  BaseAddr = (USHORT)HwDeviceExtension->ulIOAddress;*/
   USHORT  SR13,SR14=0,buswidth,Done;
   SHORT   i,j,k;
   USHORT  data, TotalCapacity, PhysicalAdrOtherPage=0;
   ULONG   Addr;
   UCHAR   temp;

   int PseudoRankCapacity,PseudoTotalCapacity,PseudoAdrPinCount;
   int RankCapacity,AdrPinCount,BankNumHigh,BankNumMid,MB2Bank;
   /*int PageCapacity,PhysicalAdrHigh,PhysicalAdrHalfPage,PhysicalAdrAnotherPage;*/
   int PageCapacity,PhysicalAdrHigh,PhysicalAdrHalfPage;

   SiSSetMode(HwDeviceExtension,0x2e);

   data=SiS_GetReg1(SiS_P3c4,0x1);
   data=data|0x20;
   SiS_SetReg1(SiS_P3c4,0x01,data);                    /* Turn OFF Display  */

   SiS_SetReg1(SiS_P3c4,0x13,0x00);
   SiS_SetReg1(SiS_P3c4,0x14,0xBF);
   buswidth=SiS_ChkBUSWidth_300(FBAddr);

   MB2Bank=16;
   Done=0;
   for(i=6;i>=0;i--) {
      if(Done==1) break;
      PseudoRankCapacity=1<<i;
      for(j=4;j>=1;j--) {
         if(Done==1) break;
         PseudoTotalCapacity=PseudoRankCapacity*j;
         PseudoAdrPinCount=15-j;
         if(PseudoTotalCapacity <= 64) {
            for(k=0;k<=16;k++) {
               if(Done==1) break;
               RankCapacity=buswidth*SiS_DRAMType[k][3];
               AdrPinCount=SiS_DRAMType[k][2]+SiS_DRAMType[k][0];
               if(RankCapacity==PseudoRankCapacity)
                 if(AdrPinCount<=PseudoAdrPinCount) {
                    if(j==3) {             /* Rank No */
                       BankNumHigh=RankCapacity*MB2Bank*3-1;
                       BankNumMid=RankCapacity*MB2Bank*1-1;
                    }
                    else {
                       BankNumHigh=RankCapacity*MB2Bank*j-1;
                       BankNumMid=RankCapacity*MB2Bank*j/2-1;
                    }
                    PageCapacity=(1<<SiS_DRAMType[k][1])*buswidth*4;
                    PhysicalAdrHigh =BankNumHigh;
                    PhysicalAdrHalfPage=(PageCapacity/2+PhysicalAdrHigh)%PageCapacity;
                    PhysicalAdrOtherPage=PageCapacity*SiS_DRAMType[k][2]+PhysicalAdrHigh;
                    /* Write data */
                    /*Test */
                    temp=(UCHAR)SiS_GetReg1(SiS_P3c4,0x15);
                    SiS_SetReg1(SiS_P3c4,0x15,(USHORT)(temp&0xFB));

                    temp=(UCHAR)SiS_GetReg1(SiS_P3c4,0x15);
                    SiS_SetReg1(SiS_P3c4,0x15,(USHORT)(temp|0x04));
                    /*Test */
                    TotalCapacity=SiS_DRAMType[k][3]*buswidth;
                    SR13=SiS_DRAMType[k][4];
                    if(buswidth==4) SR14=(TotalCapacity-1)|0x80;
                    if(buswidth==2) SR14=(TotalCapacity-1)|0x40;
                    if(buswidth==1) SR14=(TotalCapacity-1)|0x00;
                    SiS_SetReg1(SiS_P3c4,0x13,SR13);
                    SiS_SetReg1(SiS_P3c4,0x14,SR14);

                    Addr=FBAddr+(BankNumHigh)*64*1024+PhysicalAdrHigh;
                    *((USHORT *)(Addr)) = (USHORT) PhysicalAdrHigh;
                    Addr=FBAddr+(BankNumMid)*64*1024+PhysicalAdrHigh;
                    *((USHORT *)(Addr)) = (USHORT) BankNumMid;
                    Addr=FBAddr+(BankNumHigh)*64*1024+PhysicalAdrHalfPage;
                    *((USHORT *)(Addr)) = (USHORT) PhysicalAdrHalfPage;
                    Addr=FBAddr+(BankNumHigh)*64*1024+PhysicalAdrOtherPage;
                    *((USHORT *)(Addr))=PhysicalAdrOtherPage;

                    /* Read data */
                    Addr=FBAddr+(BankNumHigh)*64*1024+PhysicalAdrHigh;
                    data=*((USHORT *)(Addr));
                    if(data==PhysicalAdrHigh) Done=1;
                 }  /* if struct */
            }  /* for loop (k) */
         }  /* if struct */
      }  /* for loop (j) */
   }  /* for loop (i) */
}

USHORT
SiS_ChkBUSWidth_300(ULONG FBAddress)
{
   /*USHORT  data;*/
   PULONG  pVideoMemory;

   pVideoMemory = (PULONG) FBAddress;

   pVideoMemory[0] = 0x01234567L;
   pVideoMemory[1] = 0x456789ABL;
   pVideoMemory[2] = 0x89ABCDEFL;
   pVideoMemory[3] = 0xCDEF0123L;
   if (pVideoMemory[3]==0xCDEF0123L) { /*ChannelA128Bit */
     return(4);
   }
   if (pVideoMemory[1]==0x456789ABL) {  /*ChannelB64Bit */
     return(2);
   }
   return(1);
}
#endif

/* ===============  for 300 dram sizing end    =============== */

/* ===============  310 dram sizing begin ==================== */
#ifdef SIS315H

/* TW: Moved Get310DRAMType further down */

void
SiS_Delay15us(ULONG ulMicrsoSec)
{
}

void
SiS_SDR_MRS(void)
{
   USHORT  data;

   data=SiS_GetReg1(SiS_P3c4,0x16);
   data=data & 0x3F;          /*/ SR16 D7=0,D6=0 */
   SiS_SetReg1(SiS_P3c4,0x16,data);   /*/ enable mode register set(MRS) low */
   SiS_Delay15us(0x100);
   data=data | 0x80;          /*/ SR16 D7=1,D6=0 */
   SiS_SetReg1(SiS_P3c4,0x16,data);   /*/ enable mode register set(MRS) high */
   SiS_Delay15us(0x100);
}

void
SiS_DDR_MRS(void)
{
   USHORT  data;

   /* SR16 <- 1F,DF,2F,AF */

   /* enable DLL of DDR SD/SGRAM , SR16 D4=1 */
   data=SiS_GetReg1(SiS_P3c4,0x16);
   data &= 0x0F;
   data |= 0x10;
   SiS_SetReg1(SiS_P3c4,0x16,data);

   if (!(SiS_SR15[1][SiS_RAMType] & 0x10))
   {
     data &= 0x0F;
   }
   /* SR16 D7=1,D6=1 */
   data |= 0xC0;
   SiS_SetReg1(SiS_P3c4,0x16,data);
   
   /* SR16 D7=1,D6=0,D5=1,D4=0 */
   data &= 0x0F;
   data |= 0x20;
   SiS_SetReg1(SiS_P3c4,0x16,data);
   if (!(SiS_SR15[1][SiS_RAMType] & 0x10)) {
     data &= 0x0F;
   }
   /* SR16 D7=1 */
   data |= 0x80;
   SiS_SetReg1(SiS_P3c4,0x16,data);
}

void
SiS_SetDRAMModeRegister(ULONG ROMAddr)
{

    if (SiS_Get310DRAMType(ROMAddr)<2) {
      SiS_SDR_MRS();
    } else {
      /* SR16 <- 0F,CF,0F,8F */
      SiS_DDR_MRS();
    }
}

void
SiS_DisableRefresh(void)
{
   USHORT  data;

   data=SiS_GetReg1(SiS_P3c4,0x17);
   data &= 0xF8;
   SiS_SetReg1(SiS_P3c4,0x17,data);

   data=SiS_GetReg1(SiS_P3c4,0x19);
   data |= 0x03;
   SiS_SetReg1(SiS_P3c4,0x19,data);

}

void
SiS_EnableRefresh(ULONG ROMAddr)
{
   SiS_SetReg1(SiS_P3c4,0x17,SiS_SR15[2][SiS_RAMType]);  /* SR17 */
   SiS_SetReg1(SiS_P3c4,0x19,SiS_SR15[4][SiS_RAMType]);  /* SR19 */
}

void
SiS_DisableChannelInterleaving(int index,USHORT SiS_DDRDRAM_TYPE[][5])
{
   USHORT  data;

   data=SiS_GetReg1(SiS_P3c4,0x15);
   data &= 0x1F;
   switch (SiS_DDRDRAM_TYPE[index][3])
   {
     case 64: data |= 0;
              break;
     case 32: data |= 0x20;
              break;
     case 16: data |= 0x40;
              break;
     case 4:  data |= 0x60;