fesc_5554_irq.c

MPC5554处理器的初始化例程

/**************************************************************************/
/*                  C Code Variables and Definitions                      */
/**************************************************************************/
extern void       IVOR4Handler (void);
extern vuint32_t  __IV_ADDR;     /* Defined in the linker file */
extern uint32_t   IntcIsrVectorTable[];




void init_IRQ(void)
{
  asm ("lis r5, __IV_ADDR@h ");   /* IVPR = address base used with IVOR's */
  asm ("mtIVPR r5 ");
  asm ("lis r5, IVOR4Handler@h");  /* IVOR4 = address of handler */
  asm ("ori r5, r5, IVOR4Handler@l");
  asm ("mtIVOR4 r5");

  /* set up INTC */
  INTC.MCR.B.HVEN = 0;  /* Initialize INTC for software vector mode */
  INTC.MCR.B.VTES = 0;  /* Use the default vector table entry offsets of 4 bytes */
  INTC.IACKR.R = (uint32_t) &IntcIsrVectorTable[0]; /* Set INTC ISR vector table base addr. */

  /* software interrupt 4 IRQ priority = 2 */
  INTC.PSR[4].R = PRIO_SW4IRQ;
  /*INTC's current priority is 0 , all IRQ prio allowed*/
  INTC.CPR.B.PRI = 0;

}

/* call this to trig a Sw Irq */
void InvSBP_RTSTUS_OKe_SWI4(void){
   INTC.SSCIR[4].R = 2;   /* InvSBP_RTSTUS_OKe software interrupt 4 */
}
void SwIrq4ISR(void) {
  INTC.SSCIR[4].R = 1;    /* Clear channel's flag */
}

void emiosCh0ISR(void) {EMIOS.CH[0].CSR.B.FLAG=1;}
void emiosCh1ISR(void) {EMIOS.CH[1].CSR.B.FLAG=1;}
void emiosCh2ISR(void) {EMIOS.CH[2].CSR.B.FLAG=1;}
void emiosCh3ISR(void) {EMIOS.CH[3].CSR.B.FLAG=1;}
void emiosCh4ISR(void) {EMIOS.CH[4].CSR.B.FLAG=1;}
void emiosCh5ISR(void) {EMIOS.CH[5].CSR.B.FLAG=1;}

void emiosCh10ISR(void) {EMIOS.CH[10].CSR.B.FLAG=1;}

  /* 两个CPU都完成MF帧接收后，FPGA触发的中断 */
void emiosCh6ISR(void) {
  MF_SPI_ALL_DONE_daemon();	
	EMIOS.CH[6].CSR.B.FLAG=1;
}

   /* FPGA触发的SPI-7接收中断 */
void emiosCh7ISR(void) {
  MF_SPI_slave_daemon();
  EMIOS.CH[7].CSR.B.FLAG=1;
}

    /* MIOS产生的主流程定时中断  */
#define MATE_CNT_REG_B0 SXC.CNT_Reg[0].B.B
#define MATE_CNT_REG_B1 SXC.CNT_Reg[1].B.B
#define MATE_CNT_REG_B2 SXC.CNT_Reg[2].B.B
#define MATE_CNT_REG_B3 SXC.CNT_Reg[3].B.B
#define SELF_CNT_REG_B0 SXC.CNT_Reg[4].B.B
#define SELF_CNT_REG_B1 SXC.CNT_Reg[5].B.B
#define SELF_CNT_REG_B2 SXC.CNT_Reg[6].B.B   
#define SELF_CNT_REG_B3 SXC.CNT_Reg[7].B.B
   
void emiosCh8ISRaaa(void)
{ vuint32_t cnt_r;
	vuint32_t cnt_w;

	SELF_CNT_REG_B3 = (uint8_t)( (hs_test_cnt>> 0) & 0xFF );
  SELF_CNT_REG_B2 = (uint8_t)( (hs_test_cnt>> 8) & 0xFF );
	SELF_CNT_REG_B1 = (uint8_t)( (hs_test_cnt>>16) & 0xFF );
	SELF_CNT_REG_B0 = (uint8_t)( (hs_test_cnt>>24) & 0xFF );
	EMIOS.CH[8].CSR.B.FLAG=1;
	cnt_r = 0;
	cnt_w = 0; 
	cnt_w  = SELF_CNT_REG_B0;	cnt_w <<= 8;
	cnt_w += SELF_CNT_REG_B1;	cnt_w <<= 8;
	cnt_w += SELF_CNT_REG_B2;	cnt_w <<= 8;
	cnt_w += SELF_CNT_REG_B3;	
	cnt_r  = MATE_CNT_REG_B0;	cnt_r <<= 8;
	cnt_r += MATE_CNT_REG_B1;	cnt_r <<= 8;
	cnt_r += MATE_CNT_REG_B2;	cnt_r <<= 8;
	cnt_r += MATE_CNT_REG_B3;
  printp(send_c_ESCIA,"%8X:%8X  --> %8d\n\r",cnt_w,cnt_r,abs(cnt_w-cnt_r));
} 


   
void emiosCh8ISR(void) {
  //SYS_TICK_Daemon();
  printp(send_c_ESCIA_dpb,"--> %d\n\r",hs_test_cnt);
  EMIOS.CH[8].CSR.B.FLAG=1;  
}

    /* MIOS产生的SPI发送扫描中断  */
void emiosCh9ISR(void)
{
  //FPGA_SPI_master_daemon();
  //MT_SPI_master_daemon();
  ESCIA_out_daemon();
  EMIOS.CH[9].CSR.B.FLAG=1;
}