📄 mpc5500_ccdcfg.c
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/* INPUT NOTES : PA_A, OBE_A, IBE_A, DSC_A, ODE_A, HYS_A, */
/* SRC_A, WPE_A, WPS_A */
/* RETURN NOTES : None */
/* WARNING : Address PCRs 4:27 are automatically written in */
/* this function. */
/* 1 PCR is set per 16-bit register write. */
/******************************************************************/
void cfg_PCR_ADDR(uint16_t PA_A, uint16_t OBE_A, uint16_t IBE_A,
uint16_t DSC_A, uint16_t ODE_A, uint16_t HYS_A,
uint16_t SRC_A, uint16_t WPE_A, uint16_t WPS_A)
{
uint8_t PCRNUM;
for (PCRNUM=4; PCRNUM <=27; PCRNUM++)
{
SIU.PCR[PCRNUM].R = (PA_A | OBE_A | IBE_A | DSC_A | ODE_A | \
HYS_A | SRC_A | WPE_A | WPS_A);
}
}
/******************************************************************/
/* FUNCTION : cfg_PCR_DATA */
/* PURPOSE : This function configures PCRs for 16 Data pins. */
/* */
/* INPUT NOTES : PA_D, OBE_D, IBE_D, DSC_D, ODE_D, HYS_D, */
/* SRC_D, WPE_D, WPS_D, DATA_BITS */
/* RETURN NOTES : None */
/* WARNING : For DATA[0:15] DATA_BITS must = 0; PCR[28:43] */
/* For DATA[16:31] DATA_BITS must = 16; PCR[44:59] */
/* 1 PCR is set per 16-bit register write. */
/******************************************************************/
void cfg_PCR_DATA(uint16_t PA_D, uint16_t OBE_D, uint16_t IBE_D,
uint16_t DSC_D, uint16_t ODE_D, uint16_t HYS_D,
uint16_t SRC_D, uint16_t WPE_D, uint16_t WPS_D,
uint8_t DATA_BITS)
{
uint8_t PCRNUM; /* PCRNUM starts at either 28 or 44 */
/* 1 PCR is set per 16-bit write */
for (PCRNUM=28+DATA_BITS; PCRNUM<(44+DATA_BITS); PCRNUM++)
{
SIU.PCR[PCRNUM].R = (PA_D | OBE_D | IBE_D | DSC_D | ODE_D | \
HYS_D | SRC_D | WPE_D | WPS_D);
}
}
/**********************************************************************/
/* FUNCTION : cfg_PCR_CTRL */
/* PURPOSE : This function configures the module before any */
/* chip select configuration */
/* INPUT NOTES : PA_C, OBE_C, IBE_C, DSC_C, ODE_C, HYS_C, */
/* SRC_C, WPE_C, WPS_C, FRST_PCR, PCR_CNT */
/* RETURN NOTES : None */
/* WARNING : FRST_PCR is the first PCR written. */
/* PCR_CNT is the number of 16-bit PCR register writes.*/
/* 1 PCR is set per 16-bit register write. */
/**********************************************************************/
void cfg_PCR_CTRL(uint16_t PA_C, uint16_t OBE_C, uint16_t IBE_C, \
uint16_t DSC_C, uint16_t ODE_C, uint16_t HYS_C, \
uint16_t SRC_C, uint16_t WPE_C, uint16_t WPS_C, \
uint8_t FRST_PCR, uint8_t PCR_CNT)
{
uint8_t PCRNUM;
for (PCRNUM=FRST_PCR; PCRNUM<(FRST_PCR+PCR_CNT); PCRNUM++) /* PCRNUM = FRST_PCR to FRST_PCR+PCR_CNT */
{
SIU.PCR[PCRNUM].R = (PA_C | OBE_C | IBE_C | DSC_C | ODE_C | \
HYS_C | SRC_C | WPE_C | WPS_C);
/* 1 PCR is set per 16-bit line */
}
}
/**************************************************************************/
/* Beginning of EBI functions */
/**************************************************************************/
/******************************************************************/
/* FUNCTION : cfg_EBI_mod */
/* PURPOSE : This function configures the module before any */
/* chip select configuration */
/* INPUT NOTES : SIZEN_val,SIZE_val,ACGE_val,EXTM_val, */
/* EARB_val,EARP_val,MDIS_val,DBM_val */
/* RETURN NOTES : None */
/* WARNING : None */
/******************************************************************/
void cfg_EBI_mod(uint32_t SIZEN_val, uint32_t SIZE_val, uint32_t ACGE_val,
uint32_t EXTM_val, uint32_t EARB_val, uint32_t EARP_val,
uint32_t MDIS_val, uint32_t DBM_val)
{
EBI.MCR.R = (SIZEN_val | SIZE_val | ACGE_val | EXTM_val | \
EARB_val | EARP_val | MDIS_val | DBM_val);
}
/******************************************************************/
/* FUNCTION : cfg_EBI_BRn */
/* PURPOSE : This function configures the EBI chip select */
/* base register. */
/* INPUT NOTES : CS_val,BM_val,PS_val,BL_val,WEBS_val,TBDIP_val, */
/* BI_val, V_val */
/* RETURN NOTES : None */
/* WARNING : None */
/******************************************************************/
void cfg_CSn_BR(uint8_t CS_val, uint32_t BM_val, uint32_t PS_val,
uint32_t BL_val, uint32_t WEBS_val, uint32_t TBDIP_val,
uint32_t BI_val, uint32_t V_val)
{
EBI.CS[CS_val].BR.R = (BM_val | PS_val | BL_val | WEBS_val | \
TBDIP_val | BI_val | V_val);
}
/******************************************************************/
/* FUNCTION : cfg_EBI_ORn */
/* PURPOSE : This function configures the EBI chip select */
/* option register. */
/* INPUT NOTES : CS_val, AM_val, SCY_val, BSCY_val */
/* RETURN NOTES : None */
/* WARNING : None */
/******************************************************************/
void cfg_CSn_OR(uint8_t CS_val, uint32_t AM_val, uint32_t SCY_val,
uint32_t BSCY_val)
{
EBI.CS[CS_val].OR.R = ( AM_val | SCY_val | BSCY_val );
}
/**************************************************************************/
/* End of EBI functions */
/**************************************************************************/
/**************************************************************************/
/* FUNCTION : cfg_PBRIDGE */
/* PURPOSE : This function configures PBRIDGE A and B master */
/* privilege and peripheral access control. */
/* Default settings are used. */
/* INPUT NOTES : PBA_MPCR,PBA_PACR0,PBA_OPACRn (where n=0,1,2) */
/* PBB_MPCR,PBB_PACRn,PBB_OPACRm (where n=0,2 m=0,1,2,3) */
/* Inputs are user defined mpc5500_ccdcfg.h */
/* RETURN NOTES : None */
/* WARNING : Reference: MPC5554 RM chapter 5.3 */
/* MPCR default value = 0x77770000; */
/* PACRn & OPACRn default value = 0x44444444 */
/**************************************************************************/
void cfg_PBRIDGE()
{
/* Settings for the PBRIDGE_A */
PBRIDGE_A.MPCR.R = PBA_MPCR;
PBRIDGE_A.PACR0.R = PBA_PACR0;
PBRIDGE_A.OPACR0.R = PBA_OPACR0;
PBRIDGE_A.OPACR1.R = PBA_OPACR1;
PBRIDGE_A.OPACR2.R = PBA_OPACR2;
/* Settings for the PBRIDGE_B */
PBRIDGE_B.MPCR.R = PBB_MPCR;
PBRIDGE_B.PACR0.R = PBB_PACR0;
PBRIDGE_B.PACR2.R = PBB_PACR2;
PBRIDGE_B.OPACR0.R = PBB_OPACR0;
PBRIDGE_B.OPACR1.R = PBB_OPACR1;
PBRIDGE_B.OPACR2.R = PBB_OPACR2;
PBRIDGE_B.OPACR3.R = PBB_OPACR3;
} /* End of cfg_PBRIDGE */
/*************************************************************************/
/* FUNCTION : cfg_XBAR */
/* PURPOSE : This function configures the Cross Bar (XBAR) master */
/* channel priorities and slave port configurations. */
/* Default settings are used. */
/* INPUT NOTES : MPRn_MST2,MPRn_MST1,MPRn_MST0 (where n=0,1,3,6,7) */
/* SGPCRn_RO, SGPCRn_ARB, SGPCRn_PCTL, SGPCRn_PARK */
/* (where n=0,1,3,6,7) */
/* Inputs are user defined mpc5500_ccdcfg.h */
/* RETURN NOTES : None */
/* WARNING : MPRn default value = 0x00000210 */
/* SGPCRn default value = 0x00000000 */
/*************************************************************************/
void cfg_XBAR()
{
/* Priority settings for the masters on each Cross-Bar channel */
/* b00 = highest priority; b11 = lowest priority */
/* Master2=2; Master1=1; Master0=0(highest priority) */
XBAR.MPR0.R = ( MPR0_MST2 | MPR0_MST1 | MPR0_MST0 );
XBAR.MPR1.R = ( MPR1_MST2 | MPR1_MST1 | MPR1_MST0 );
XBAR.MPR3.R = ( MPR3_MST2 | MPR3_MST1 | MPR3_MST0 );
XBAR.MPR6.R = ( MPR6_MST2 | MPR6_MST1 | MPR6_MST0 );
XBAR.MPR7.R = ( MPR7_MST2 | MPR7_MST1 | MPR7_MST0 );
/* Configuration settings for Slave channels */
/* All Slave ports can be written as configured */
/* XBAR_SGPCRs are set to: Read/Write; arbitration fixed; */
/* Park on master port 0 */
/* These are the default settings. */
XBAR.SGPCR0.R = ( SGPCR0_RO | SGPCR0_ARB | SGPCR0_PCTL | SGPCR0_PARK );
XBAR.SGPCR1.R = ( SGPCR1_RO | SGPCR1_ARB | SGPCR1_PCTL | SGPCR1_PARK );
XBAR.SGPCR3.R = ( SGPCR3_RO | SGPCR3_ARB | SGPCR3_PCTL | SGPCR3_PARK );
XBAR.SGPCR6.R = ( SGPCR6_RO | SGPCR6_ARB | SGPCR6_PCTL | SGPCR6_PARK );
XBAR.SGPCR7.R = ( SGPCR7_RO | SGPCR7_ARB | SGPCR7_PCTL | SGPCR7_PARK );
} /* End of cfg_XBAR */
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