mpc5500_ccdcfg.c

MPC5554处理器的初始化例程

/**************************************************************************/
/* FILE NAME: mpc5500_ccdcfg.c               COPYRIGHT (c) Freescale 2004 */
/*                                                All Rights Reserved     */
/* DESCRIPTION:                                                           */
/* This file contains functions for the MPC5500 assembly configuration.   */
/* The user does not need to make any changes in this file.               */
/* The user will change function field values in mpc5500_ccdcfg.h.        */
/* Choices for field values are found in mpc5500_ccdcfg.h.                */
/*========================================================================*/
/* REV      AUTHOR       DATE       DESCRIPTION OF CHANGE                 */
/* ---   -----------   ----------   ---------------------                 */
/* 0.1   J. Yokubaitis 24/Nov/03     Initial version                      */
/* 0.2   G. Jackson    15/Mar/04     Split into C code configuration      */
/* 0.3   G. Jackson    15/Apr/04     C application functions removed      */
/* 0.4   G. Jackson    13/May/04     Added CS2 and CS3 initializations    */
/* 0.5   G. Jackson    08/Jun/04     Added PCR initialization for the     */
/*                                    external bus and chip select 0 (CS0)*/
/*                                    with external boot config option    */
/*                                    control.                            */
/* 0.6   G. Jackson    10/Jun/04     Changed EXT_BOOT to INT_BOOT as a    */
/*                                   config option in mpc5500_usrccdcfg.h.*/
/* 1.0   G. Jackson    30/Jun/04     Changed INT_BOOT to I_EXT_BUS_EN     */
/*                                    Added I_DATA_PORT_SIZE              */
/*                                    Added I_CFG_PBRG_XBAR               */
/**************************************************************************/


#include "mpc5554.h"
#include "mpc5500_usrccdcfg.h"


/***************************************************************************/
/* FUNCTION     : cfg_mpc5500ccd()                                         */
/* PURPOSE      : This function provides "C" code configuration for the    */
/*                 MPC5500 family device. Previous initialization has set  */
/*                 up the FMPLL clock speed, internal SRAM and the stack.  */
/*                 The cfg_mpc5500ccd function completes initialization by */
/*                 making desired changes to the XCLKS, EBI chip selects,  */
/*                 with default settings for PBRIDGE_A, PBRIDGE_B, and the */
/*                 XBAR.                                                   */
/*                                                                         */
/*                 In cases where (numerous) alternative initializations   */
/*                 are desired, a sample configuration is included here.   */  
/*                 Actual initialization required for a specific system    */ 
/*                 remains the responsibility of the developer.            */
/* INPUT NOTES  : (from mpc5500_usrccdcfg.h) I_CFG_XCLKS, I_EXT_BUS_EN,    */
/*                  I_CFG_PBRG_XBAR                                        */
/* RETURN NOTES : None                                                     */
/* WARNING      : An external boot will configure CS0, the address bus,    */
/*                 and the data bus; I_EXT_BUS_EN = YES will reconfigure   */
/*                 the external bus with settings in mpc5500_usrccdcfg.h.  */                        
/***************************************************************************/

/* MPC5500 initialization functions */
void cfg_mpc5500ccd() {
/*void cfg_mpc5500ccd(uint8_t External_Boot) { */
   if(I_CFG_XCLKS) {   /* Option to change external clock speeds */
     cfg_XCLKS();      /* Set up the External Clock speeds */
    }                  /* end I_CFG_XCLKS */

   if(I_EXT_BUS_EN) {  /* Set up external bus if enabled */

     cfg_PCR();        /* Set up Pad Configuration Registers for external bus */ 
     
     cfg_EBI();        /* Configure the External Bus Interface Chip Selects */

    }                  /* end external bus enable */ 

   if(I_CFG_PBRG_XBAR) {  /* Skip if not configuring PBRIDGEs or XBAR   */
                          /* NOTE: These steps may not be necessary.    */
                          /*       The user must know the exact effect. */

     cfg_PBRIDGE();    /* Configure PBRIDGE_A and PBRIDGE_B. */

     cfg_XBAR();       /* Configure the XBAR master/slave channel priorities. */
    }


} /* End of cfg_mpc5500ccd()  */


/**************************************************************************/
/*                       C Code Functions                                 */
/**************************************************************************/


/*************************************************************************/
/* FUNCTION     : cfg_XCLKS                                              */
/* PURPOSE      : This function configures the external clocks (CLKOUT   */
/*                 and ENGCLK). The PCRs are also set for these 2 pins.  */
/* INPUT NOTES  : I_CFG_XCLKS -- used to permit external clock changes.  */
/*                               Defined in mpc5500_usrccdcfg.h          */
/* RETURN NOTES : None                                                   */
/* WARNING      : None                                                   */
/*************************************************************************/

void cfg_XCLKS() 
{

/* This function configures the external clocks */
/*   Engineering clock is set to divide by 128    */
/*   CLKOUT is set to divide-by-2                 */

/* Set the value for Pad Configuration Register (PCR214) for ENGCLK */
    SIU.PCR[214].R = (OBE_ENGCLK_VAL | DSC_ENGCLK_VAL);


/* Set the value for Pad Configuration Register (PCR229) for CLKOUT */
    SIU.PCR[229].R = (OBE_CLKOUT_VAL | DSC_CLKOUT_VAL);

/* Set the value for the external clocks */

    SIU.ECCR.R = (ECCR_ENGDIV | ECCR_EBTS | ECCR_EBDF);

} /* End of cfg_XCLKS  */

/******************************************************************/
/* FUNCTION     : cfg_PCR                                         */
/* PURPOSE      : This function configures the SIU PCR's for      */
/*                  external bus operation.                       */
/* INPUT NOTES  : None                                            */
/* RETURN NOTES : None                                            */
/* WARNING      : This function will be skipped if there is       */
/*                 an external boot.                              */
/*                Entries for *_C1 and *_C2 are control variables */
/*                Entries for *_CG1 through *_CG4 are Control     */
/*                 Group numbers. A Control Group is independent  */
/*                 of the control variables (*_C1,etc.)           */
/* ****************************************************************/
void cfg_PCR()
{

/* This function configures the Pad Configuration Registers (PCR's) for ADDR[8:31] */
    cfg_PCR_ADDR(PA_A_VAL, OBE_A_VAL, IBE_A_VAL, DSC_A_VAL, ODE_A_VAL, HYS_A_VAL, SRC_A_VAL, WPE_A_VAL, WPS_A_VAL);

/* This function configures the Pad Configuration Registers (PCR's) for DATA[0:15] */
    cfg_PCR_DATA(PA_DL, OBE_DL, IBE_DL, DSC_DL, ODE_DL, HYS_DL, SRC_DL, WPE_DL, WPS_DL, DATA_BYT_MSB);

/* This function configures the Pad Configuration Registers (PCR's) for DATA[16:31] */
/*  This function call is not needed for a 16-bit external data bus */
  if(I_DATA_PORT_SIZE == 32) {
    cfg_PCR_DATA(PA_DH, OBE_DH, IBE_DH, DSC_DH, ODE_DH, HYS_DH, SRC_DH, WPE_DH, WPS_DH, DATA_BYT_LSB);
   }

/* This function configures the Pad Configuration Registers (PCR's) for Control */
    cfg_PCR_CTRL(PA_C1, OBE_C1, IBE_C1, DSC_C1, ODE_C1, HYS_C1, SRC_C1, WPE_C1, WPS_C1, FRST_PCR_CG1, PCR_CNT_CG1);

/* This function configures the Pad Configuration Registers (PCR's) for Control */
    cfg_PCR_CTRL(PA_C2, OBE_C2, IBE_C2, DSC_C2, ODE_C2, HYS_C2, SRC_C2, WPE_C2, WPS_C2,FRST_PCR_CG2, PCR_CNT_CG2);
    cfg_PCR_CTRL(PA_C2, OBE_C2, IBE_C2, DSC_C2, ODE_C2, HYS_C2, SRC_C2, WPE_C2, WPS_C2,FRST_PCR_CG3, PCR_CNT_CG3);
    cfg_PCR_CTRL(PA_C2, OBE_C2, IBE_C2, DSC_C2, ODE_C2, HYS_C2, SRC_C2, WPE_C2, WPS_C2,FRST_PCR_CG4, PCR_CNT_CG4);

}

/*****************************************************************/
/* FUNCTION     : cfg_EBI                                        */
/* PURPOSE      : This function configures the EBI Chip Selects. */
/* INPUT NOTES  : None                                           */
/* RETURN NOTES : None                                           */
/* WARNING      : None                                           */
/* ***************************************************************/
void cfg_EBI()
{
 /*This function configures the module before any chip select configuration */
      cfg_EBI_mod(SIZEN_VAL, SIZE_VAL, ACGE_VAL, EXTM_VAL, EARB_VAL, EARP_VAL, MDIS_VAL, DBM_VAL);

/* This function configures the base register for a CS_0 */
    cfg_CSn_BR(CS_0, CS0_BA, CS0_PS, CS0_BL, CS0_WEBS, CS0_TBDIP, CS0_BI, CS0_V);

/* This function configures the option register for CS_0 */
/*   Chip Select 0 is targeted for external Flash with wait states */
    cfg_CSn_OR(CS_0, CS0_AM, CS0_SCY, CS0_BSCY);

/* This function configures the base register for a CS_1 */
    cfg_CSn_BR(CS_1, CS1_BA, CS1_PS, CS1_BL, CS1_WEBS, CS1_TBDIP, CS1_BI, CS1_V);

/* This function configures the option register for CS_1 */
/*   Chip Select 1 is targeted for external RAM with 4 wait states */
    cfg_CSn_OR(CS_1, CS1_AM, CS1_SCY, CS1_BSCY);

/* This function configures the base register for a CS_2 */
    cfg_CSn_BR(CS_2, CS2_BA, CS2_PS, CS2_BL, CS2_WEBS, CS2_TBDIP, CS2_BI, CS2_V);

/* This function configures the option register for CS_2 */
/*   Chip Select 1 is targeted for external RAM with 0 wait states */
    cfg_CSn_OR(CS_2, CS2_AM, CS2_SCY, CS2_BSCY);

/* This function configures the base register for a CS_3 */
    cfg_CSn_BR(CS_3, CS3_BA, CS3_PS, CS3_BL, CS3_WEBS, CS3_TBDIP, CS3_BI, CS3_V);

/* This function configures the option register for CS_3 */
/*   Chip Select 1 is targeted for external RAM with 0 wait states */
    cfg_CSn_OR(CS_3, CS3_AM, CS3_SCY, CS3_BSCY);

} /* End of cfg_EBI */

/**************************************************************************/
/*                    Beginning of SIU functions                          */
/**************************************************************************/

/******************************************************************/
/* FUNCTION     : cfg_PCR_ADDR                                    */
/* PURPOSE      : This function configures the module before any  */ 
/*                chip select configuration                       */