📄 mpc5500_asmcfg.s
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dcbz r0, r5 # Establish address in cache for 32 bytes and zero
dcbtls 0, r0, r5 # Lock the address into the cache
addi r5, r5, 32 # Increment to start of next cache line (+32 bytes)
bdnz _cache_loop # Decrement the counter (CTR), branch if nonzero
# Set the stack pointer
lis r1, (__SP_INIT-0x10)@h
ori r1, r1, (__SP_INIT-0x10)@l
blr
# End of cfg_STACK
#*****************************************************************************/
# FUNCTION : cfg_PNTRS */
# PURPOSE : This function initializes register pointers for small data */
# (.sbss) in R13 and small data2 (.sdata2) in R2. */
# */
# INPUT NOTES : _SDA_BASE_, _SDA2_BASE_ (defined by the linker EABI) */
# RETURN NOTES : None */
# WARNING : Registers used: R13(to set .sdata pointer ), */
# R2 (to set .sdata2 pointer) */
# The BASE addresses are offset by 0x8000 for CW, GHS, P&E */
# and offset by 0x7FF0 for Diab to simplify access to small */
# data. */
#*****************************************************************************/
cfg_PNTRS:
# Set the small data (.sbss) pointer
lis r13, (_SDA_BASE_)@h
ori r13, r13, (_SDA_BASE_)@l
# Set the small data2 (.sdata2) pointer
lis r2, (_SDA2_BASE_)@h
ori r2, r2, (_SDA2_BASE_)@l
blr
# End of cfg_PNTRS
#*****************************************************************************/
# FUNCTION : cfg_ROMCPY */
# PURPOSE : This function copies initialized data from Flash to SRAM */
# for the ".data" and ".sdata" sections. */
# */
# INPUT NOTES : __DATA_ROM -- defined by the linker EABI */
# __ROM_COPY_SIZE -- Flash area size, in bytes, to be copied */
# into SRAM. */
# __SRAM_CPY_START -- Start of ".data" section */
# CPY_OFFSET -- (=1) defined in mpc5500_defs.inc. 1 byte */
# offset to next data byte address. */
# RETURN NOTES : None */
# WARNING : Registers used: R10 -- to set .data or .sdata ROM pointer */
# R9 -- to hold remaining ROM_COPY_SIZE bytes */
# R5 -- to set SRAM pointer */
# R4 -- hold the copy data */
# */
#*****************************************************************************/
cfg_ROMCPY:
# Set GPR9 to the count of the SRAM load size
lis r9, __ROM_COPY_SIZE@ha # Load upper SRAM load size (# of bytes) into R9
addic. r9,r9, __ROM_COPY_SIZE@l # Load lower SRAM load size into R9
# The "." sets the condition flag
beq ROMCPYEND # Exit cfg_ROMCPY if size is zero
mtctr r9 # Store # of bytes to be moved in spr CTR
lis r10, __DATA_ROM@ha # Load address of first SRAM load into R10
addi r10,r10, __DATA_ROM@l # Load lower address of SRAM load into R10
subi r10,r10, CPY_OFFSET # Decrement address to prepare for ROMCPYLOOP
# Load SRAM base address (__SRAM_CPY_START) for loading instructions into R5
# (__SRAM_CPY_START = ADDR(.data))
lis r5, __SRAM_CPY_START@h # Load upper SRAM address into R5
ori r5, r5, __SRAM_CPY_START@l # Load lower SRAM address into R5
subi r5, r5, CPY_OFFSET # Decrement address to prepare for ROMCPYLOOP
ROMCPYLOOP:
lbzu r4, CPY_OFFSET(r10) # Load data byte at R10 into R4,incrementing (update) ROM address
stbu r4, CPY_OFFSET(r5) # Store R4 data byte into SRAM at R5 and update SRAM address
bdnz ROMCPYLOOP # Branch if more bytes to load from ROM
ROMCPYEND:
blr
# End of cfg_ROMCPY
#*************************************************************************/
# MMU Functions */
#*************************************************************************/
#*****************************************************************************/
# FUNCTION : cfg_MMU */
# PURPOSE : This function modifies the MMU TLB (translation lookaside */
# buffer) table by writing to the appropriate MAS registers. */
# INPUT NOTES : Requires SPRs defined and a data table for the TLB entries */
# mmu_tlb0 through mmu_tlb11, mmu_tlb15 from */
# mpc5500_usrdefs.inc. */
# RETURN NOTES : None */
# WARNING : Registers used: R3,R5. Commands "msync" and "isync" are not */
# required around the tlbwe since we are at configuration and */
# other background operations cannot be active. */
#*****************************************************************************/
cfg_MMU:
#***************************************************/
# setup MMU */
#***************************************************/
# Change the TLB15 BAM in Flash size to 1M.
lis r3, mmu_tlb15@h # base address of MAS Constants
ori r3,r3, mmu_tlb15@l
lwz r5,0(r3) # Get MAS0 value
mtspr mas0,r5 # mtspr MAS0,r5
lwzu r5,4(r3) # Get MAS1 value
mtspr mas1,r5 # mtspr MAS1,r5
lwzu r5,4(r3) # Get MAS2 value
mtspr mas2,r5 # mtspr MAS2,r5
lwzu r5,4(r3) # Get MAS3 value
mtspr mas3,r5 # mtspr MAS3,r5
tlbwe # Write the entry to the TLB
# Change the TLB0 PBRIDGE_B size to 1M.
lis r3, mmu_tlb0@h # base address of MAS Constants
ori r3,r3, mmu_tlb0@l
lwz r5,0(r3) # Get MAS0 value
mtspr mas0,r5 # mtspr MAS0,r5
lwzu r5,4(r3) # Get MAS1 value
mtspr mas1,r5 # mtspr MAS1,r5
lwzu r5,4(r3) # Get MAS2 value
mtspr mas2,r5 # mtspr MAS2,r5
lwzu r5,4(r3) # Get MAS3 value
mtspr mas3,r5 # mtspr MAS3,r5
tlbwe # Write the entry to the TLB
# Change the TLB1 Flash (1) size to 1M. Split into 5 areas.
lis r3, mmu_tlb1@h # base address of MAS Constants
ori r3,r3, mmu_tlb1@l
lwz r5,0(r3) # Get MAS0 value
mtspr mas0,r5 # mtspr MAS0,r5
lwzu r5,4(r3) # Get MAS1 value
mtspr mas1,r5 # mtspr MAS1,r5
lwzu r5,4(r3) # Get MAS2 value
mtspr mas2,r5 # mtspr MAS2,r5
lwzu r5,4(r3) # Get MAS3 value
mtspr mas3,r5 # mtspr MAS3,r5
msync # synchronize for running out of Flash
tlbwe # Write the entry to the TLB
isync # synchronize for running out of Flash
# Change the TLB2 External Flash size to 4M.
lis r3, mmu_tlb2@h # base address of MAS Constants
ori r3,r3, mmu_tlb2@l
lwz r5,0(r3) # Get MAS0 value
mtspr mas0,r5 # mtspr MAS0,r5
lwzu r5,4(r3) # Get MAS1 value
mtspr mas1,r5 # mtspr MAS1,r5
lwzu r5,4(r3) # Get MAS2 value
mtspr mas2,r5 # mtspr MAS2,r5
lwzu r5,4(r3) # Get MAS3 value
mtspr mas3,r5 # mtspr MAS3,r5
tlbwe # Write the entry to the TLB
# Change the TLB3 SRAM size to 64K.
lis r3, mmu_tlb3@h # base address of MAS Constants
ori r3,r3, mmu_tlb3@l
lwz r5,0(r3) # Get MAS0 value
mtspr mas0,r5 # mtspr MAS0,r5
lwzu r5,4(r3) # Get MAS1 value
mtspr mas1,r5 # mtspr MAS1,r5
lwzu r5,4(r3) # Get MAS2 value
mtspr mas2,r5 # mtspr MAS2,r5
lwzu r5,4(r3) # Get MAS3 value
mtspr mas3,r5 # mtspr MAS3,r5
tlbwe # Write the entry to the TLB
# Change the TLB4 PBRIDGE_A size to 1M.
lis r3, mmu_tlb4@h # base address of MAS Constants
ori r3,r3, mmu_tlb4@l
lwz r5,0(r3) # Get MAS0 value
mtspr mas0,r5 # mtspr MAS0,r5
lwzu r5,4(r3) # Get MAS1 value
mtspr mas1,r5 # mtspr MAS1,r5
lwzu r5,4(r3) # Get MAS2 value
mtspr mas2,r5 # mtspr MAS2,r5
lwzu r5,4(r3) # Get MAS3 value
mtspr mas3,r5 # mtspr MAS3,r5
tlbwe # Write the entry to the TLB
## Change the TLB5 to invalid to turn off duplicate entries for internal Flash
lis r3, mmu_tlb5@h # base address of MAS Constants
ori r3,r3, mmu_tlb5@l
lwz r5,0(r3) # Get MAS0 value
mtspr mas0,r5 # mtspr MAS0,r5
lwzu r5,4(r3) # Get MAS1 value
mtspr mas1,r5 # mtspr MAS1,r5
tlbwe # Write the entry to the TLB
# Change the TLB6 Flash (2) size to 256K.
lis r3, mmu_tlb6@h # base address of MAS Constants
ori r3,r3, mmu_tlb6@l
lwz r5,0(r3) # Get MAS0 value
mtspr mas0,r5 # mtspr MAS0,r5
lwzu r5,4(r3) # Get MAS1 value
mtspr mas1,r5 # mtspr MAS1,r5
lwzu r5,4(r3) # Get MAS2 value
mtspr mas2,r5 # mtspr MAS2,r5
lwzu r5,4(r3) # Get MAS3 value
mtspr mas3,r5 # mtspr MAS3,r5
tlbwe # Write the entry to the TLB
# Change the TLB7 Flash (3) size to 256K.
lis r3, mmu_tlb7@h # base address of MAS Constants
ori r3,r3, mmu_tlb7@l
lwz r5,0(r3) # Get MAS0 value
mtspr mas0,r5 # mtspr MAS0,r5
lwzu r5,4(r3) # Get MAS1 value
mtspr mas1,r5 # mtspr MAS1,r5
lwzu r5,4(r3) # Get MAS2 value
mtspr mas2,r5 # mtspr MAS2,r5
lwzu r5,4(r3) # Get MAS3 value
mtspr mas3,r5 # mtspr MAS3,r5
tlbwe # Write the entry to the TLB
# Change the TLB8 Flash (4) size to 256K.
lis r3, mmu_tlb8@h # base address of MAS Constants
ori r3,r3, mmu_tlb8@l
lwz r5,0(r3) # Get MAS0 value
mtspr mas0,r5 # mtspr MAS0,r5
lwzu r5,4(r3) # Get MAS1 value
mtspr mas1,r5 # mtspr MAS1,r5
lwzu r5,4(r3) # Get MAS2 value
mtspr mas2,r5 # mtspr MAS2,r5
lwzu r5,4(r3) # Get MAS3 value
mtspr mas3,r5 # mtspr MAS3,r5
tlbwe # Write the entry to the TLB
# Change the TLB9 Flash (5) size to 256K.
lis r3, mmu_tlb9@h # base address of MAS Constants
ori r3,r3, mmu_tlb9@l
lwz r5,0(r3) # Get MAS0 value
mtspr mas0,r5 # mtspr MAS0,r5
lwzu r5,4(r3) # Get MAS1 value
mtspr mas1,r5 # mtspr MAS1,r5
lwzu r5,4(r3) # Get MAS2 value
mtspr mas2,r5 # mtspr MAS2,r5
lwzu r5,4(r3) # Get MAS3 value
mtspr mas3,r5 # mtspr MAS3,r5
tlbwe # Write the entry to the TLB
# Add TLB10 definition for Stack in CACHE size to 4K.
lis r3, mmu_tlb10@h # base address of MAS Constants
ori r3,r3, mmu_tlb10@l
lwz r5,0(r3) # Get MAS0 value
mtspr mas0,r5 # mtspr MAS0,r5
lwzu r5,4(r3) # Get MAS1 value
mtspr mas1,r5 # mtspr MAS1,r5
lwzu r5,4(r3) # Get MAS2 value
mtspr mas2,r5 # mtspr MAS2,r5
lwzu r5,4(r3) # Get MAS3 value
mtspr mas3,r5 # mtspr MAS3,r5
tlbwe # Write the entry to the TLB
# Change the TLB11 External SRAM size to 4M.
lis r3, mmu_tlb11@h # base address of MAS Constants
ori r3,r3, mmu_tlb11@l
lwz r5,0(r3) # Get MAS0 value
mtspr mas0,r5 # mtspr MAS0,r5
lwzu r5,4(r3) # Get MAS1 value
mtspr mas1,r5 # mtspr MAS1,r5
lwzu r5,4(r3) # Get MAS2 value
mtspr mas2,r5 # mtspr MAS2,r5
lwzu r5,4(r3) # Get MAS3 value
mtspr mas3,r5 # mtspr MAS3,r5
tlbwe # Write the entry to the TLB
# Change the TLB14 Shadow Block size to 4K.
lis r3, mmu_tlb14@h # base address of MAS Constants
ori r3,r3, mmu_tlb14@l
lwz r5,0(r3) # Get MAS0 value
mtspr mas0,r5 # mtspr MAS0,r5
lwzu r5,4(r3) # Get MAS1 value
mtspr mas1,r5 # mtspr MAS1,r5
lwzu r5,4(r3) # Get MAS2 value
mtspr mas2,r5 # mtspr MAS2,r5
lwzu r5,4(r3) # Get MAS3 value
mtspr mas3,r5 # mtspr MAS3,r5
tlbwe # Write the entry to the TLB
blr
# End of cfg_MMU
#*************************************************************************
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