📄 mpc5500_asmcfg.s
字号:
# FMPLL.SYNCR.B.LOLRE = 1;
# Disable interrupt on loss of lock
# FMPLL.SYNCR.B.LOLIRQ = 0;
# Address for FMPLL_SYNCR is in R5
.if I_LOSSLRST # if .equ I_LOSSLRST = 1?
lwz r6,0(r5) # Load value of FMPLL_SYNCR into R6
oris r6,r6,0x0002 # Load the OR of LOLRE into R5 (upper)
lis r8,0xFFFF # Load upper mask for LOLIRQ FMPLL_SYNCR into R8
ori r8,r8,0xBFFF # Load lower mask for LOLIRQ FMPLL_SYNCR into R8
and r10,r6, r8 # Mask out the LOLIRQ bit into R10
stw r10,0(r5) # Load into FMPLL_SYNCR from R10
.endif
# Enable reset on loss of clock (Disable LOCIRQ)
# FMPLL.SYNCR.B.LOCRE = 1;
# Disable interrupt on loss of clock
# FMPLL.SYNCR.B.LOCIRQ = 0;
# Address for FMPLL_SYNCR is in R5
.if I_LOSSCRST
lwz r6,0(r5) # Load value of FMPLL_SYNCR into R6
oris r6,r6,0x0001 # Load the OR of LOCRE into R5 (upper)
lis r8,0xFFFF # Load upper mask FMPLL_SYNCR into R8
ori r8,r8,0xDFFF # Load lower mask for LOCIRQ FMPLL_SYNCR into R8
and r10,r6, r8 # Mask out the LOCIRQ bit into R10
stw r10,0(r5) # Load into FMPLL_SYNCR from R10
.endif
# Enable interrupt on loss of clock
# FMPLL.SYNCR.B.LOCIRQ = 1;
# Disable reset on loss of clock
# FMPLL.SYNCR.B.LOCRE = 0;
# Address for FMPLL_SYNCR is in R5
.if I_LOCINT
lwz r6,0(r5) # Load value of FMPLL_SYNCR into R6
ori r6,r6,0x2000 # Load the OR of LOCIRQ into R5 (lower)
lis r8,0xFFFE # Load upper mask for LOCRE FMPLL_SYNCR into R8
ori r8,r8,0xFFFF # Load lower mask for FMPLL_SYNCR into R8
and r10,r6, r8 # Mask out the LOCRE bit into R10
stw r10,0(r5) # Load into FMPLL_SYNCR from R10
.endif
# Enable interrupt on loss of lock
# FMPLL.SYNCR.B.LOLIRQ = 1;
# Disable reset on loss of lock
# FMPLL.SYNCR.B.LOLRE = 0;
# Address for FMPLL_SYNCR is in R5
.if I_LOLINT
lwz r6,0(r5) # Load value of FMPLL_SYNCR into R6
ori r6,r6,0x4000 # Load the OR of LOLIRQ into R6 (lower)
lis r8,0xFFFD # Load upper mask for LOLRE FMPLL_SYNCR into R8
ori r8,r8,0xFFFF # Load lower mask for FMPLL_SYNCR into R8
and r10,r6, r8 # Mask out the LOLRE bit into R10
stw r10,0(r5) # Load into FMPLL_SYNCR from R10
.endif
FMPLL_RETURN:
blr
# End of cfg_FMPLL
#*************************************************************************/
# FUNCTION : cfg_SRAM */
# PURPOSE : This function initializes the SRAM by writing 64 bit */
# values to every SRAM location. This will set the */
# initial ECC (Error Correction Code). */
# INPUT NOTES : INT_SRAM_BASE, INT_SRAM_128BYTSEGS (INT_SRAM_SIZE >> 7) */
# RETURN NOTES : None */
# WARNING : Registers used: R5 */
#*************************************************************************/
cfg_SRAM:
# loop counter to get all of RAM
lis r5, INT_SRAM_128BYTSEGS@h # Number of 128 byte segments
ori r5, r5, INT_SRAM_128BYTSEGS@l # Number of 128 byte segments
mtctr r5 # configure control register for use with bdnz
# base address of the internal SRAM
lis r5,SRAM_BASE_ADDR@h
ori r5,r5, SRAM_BASE_ADDR@l
sram_loop:
stmw r0,0(r5) # write all 32 registers to L2RAM
addi r5,r5,128 # increment the ram ptr
bdnz sram_loop # loop for 64k of L2RAM
blr
# End of cfg_SRAM
#**************************************************************************/
# FUNCTION : cfg_FLASH */
# PURPOSE : This function reduces the wait states for internal Flash */
# and external Flash at CS0 */
# INPUT NOTES : IP_ADVANCE, __SRAM_LOAD_SIZE, __SRAM_LOAD, */
# cfg_SRAM_LOAD, FLASH_BIUCRREG, FLASH_SETTINGS, */
# CS0OR0REG, commented out: CS0_OR_OPTIONS */
# RETURN NOTES : None */
# WARNING : This SRAM space was set up by the BAM */
# Registers used: R6,R7 (Location is critical for use in */
# SRAM loads). For local use: R3,R4,R5,R10 */
# Registers R8 and R9 are used in commented example for */
# optimization of external Flash boot. */
# __SRAM_LOAD is set to ADDR(.heap) */
#**************************************************************************/
cfg_FLASH:
# Save the Link Register into R3
mflr r3
#********************************
# Prepare registers for SRAM load usage
# Enter address and settings to reduce Internal Flash wait states
# Prepare R6 and R7 to hole the FLASH_BIUCR address and wait state value
# Set R6 to hold address of FLASH_BIUCR
lis r6, FLASH_BIUCRREG@h # Load upper address of FLASH_BIUCR into R6
ori r6, r6, FLASH_BIUCRREG@l # Load lower address of FLASH_BIUCR into R6
# Set R7 to hold value of internal Flash BIU control register (FLASH_BIUCR) settings
lis r7, FLASH_SETTINGS@h # Store upper Flash BIU control
ori r7, r7, FLASH_SETTINGS@l # Store lower Flash BIU control
# If using external Flash boot or execution, external Flash wait states
# should be configured here. These are not covered here due to the
# many external configurations that can occur with external Flash.
# Example steps are below.
.if EXT_BOOT
# insert external memory wait state reduction code here
# Prepare R8 and R9 to hold the CS0 address and wait state value
# Set R8 to hold address of CS0OR0REG
# lis r8, CS0ORREG@h # Load upper address of CS0 OR0 register
# ori r8, r8, CS0ORREG@l # Load lower address of CS0 OR0 register
# Set R9 to hold value of CS0 OR0 register settings
# lis r9, CS0_OR_OPTIONS@h
# ori r9, r9, CS0_OR_OPTIONS@l
.endif
SRAMLOAD:
# Set the counter (CTR) to the count of the SRAM load size
lis r10, __SRAM_LOAD_SIZE@h # Load upper SRAM load size into R10
ori r10,r10, __SRAM_LOAD_SIZE@l # Load lower SRAM load size into R10
mtctr r10 # Move the SRAM load size into the counter
lis r10, cfg_SRAM_LOAD@ha # Load address of first SRAM load
addi r10,r10, cfg_SRAM_LOAD@l
# Load SRAM base address (__SRAM_LOAD) for loading instructions into R5
# (__SRAM_LOAD = ADDR(.heap))
lis r5, __SRAM_LOAD@h # Load upper SRAM address into R5
ori r5, r5, __SRAM_LOAD@l # Load lower SRAM address into R5
SRAMLOADLOOP:
lwz r4, 0(r10) # Load the opcode at R10 into R4
stw r4, 0(r5) # Store R4 opcode into SRAM at R5
addi r5, r5,IP_ADVANCE # Advance the SRAM address to next opcode space
addi r10, r10, IP_ADVANCE # Move address to next opcode space
bdnz SRAMLOADLOOP # Decrement the counter;
# # Branch if Counter not zero.
# Call to SRAM
CallSRAMFunction:
# Link register is saved at start of this function into R3
lis r5, __SRAM_LOAD@ha # Load upper SRAM address into R5
addi r5, r5, __SRAM_LOAD@l # Load lower SRAM address into R5
mtctr r5
bctrl
# The value of the following registers must be preserved **
# during the SRAM run: **
# R6 = Address for FLASH_BIUCR at: 0xC3F8801C **
# R7 = Data for FLASH_BIUCR at: 0x00086C35 **
# The assembler commands will be loaded as opcodes into **
# SRAM. These are located in file mpc5500_SRAM_load.s **
# Additional assembly commands may be added by the user.**
# If the length of this code is longer than 0xE0, then **
# additional space will have to be set aside in the **
# linker file for the flash_data length. **
# Return to Flash code operation
# Restore the Link Register from R3
mtlr r3
blr
# End of cfg_FLASH
#*****************************************************************************/
# FUNCTION : cfg_STACK */
# PURPOSE : This function initializes and locks a 4K Stack region */
# to be located in Cache. After the stack and the MMU */
# entries are established, C Code can be used in the */
# application. */
# INPUT NOTES : __STACK_SIZE, __SP_INIT, __SP_END, (defined in linker file) */
# CACHE_CLEAR, CACHE_SETTINGS, L1CSR0 */
# RETURN NOTES : None */
# WARNING : Registers used: R0(as 0),R1(to set stack ptr),R5, R6 */
#*****************************************************************************/
#
# Stack Size = __STACK_SIZE = (__SP_END - __SP_INIT = 4096) (0x1000) 32-bit constant
# .equ __STACK_SIZE, 0x1000 (4K is the default size) -- Defined in the linker file
# .equ __SP_INIT = 0x4001_1000 -- Defined in the linker file
# .equ __SP_END, (__SP_INIT - __STACK_SIZE) -- Defined in the linker file
#
# .equ CACHE_CLEAR,(CLFC_NO_OP | CINV_INV_OP | CE_DISABLE)
# .equ CACHE_SETTINGS, (CWM_COPYBCK | DPB_NOPUSH | CE_ENABLE)
cfg_STACK:
#****************************
# Confirm that no prior cache invalidate operation is in progress
li r6, 0x0002 # Set bit[30] in R6 (others are 0)
mfspr r5, L1CSR0 # Move L1CSR0 into R5
and r5, r5, r6 # Mask out all bits except CINV*
#P&E modification
.if __PEGNU__
cmpli 0,r5,0x0002 # Compare if CINV, bit 30, = 1
.else
cmpli r5, 0x0002 # Compare if CINV, bit 30, = 1
.endif
# cmpli r5, 0x0002 # Compare if CINV, bit 30, = 1
# wait for 134 cycles, then CINV must be cleared.
# Set up counter
lis r6, 0x0000 # Load counter value into R6
ori r6, r6, 0x0100
mtctr r6
waitCINVclear1:
bdnz waitCINVclear1 # wait for decrement counter
#****************************
# Invalidate the Cache first, just to make sure it is cleared
# To activate cache invalidate operation,
# place a "1" in the CINV bit location. (L1CSR0)
lis r5, CACHE_CLEAR@h # Load upper L1CSR0 (0x0) into R5
ori r5, r5, CACHE_CLEAR@l # Load lower L1CSR0 (CINV bit) into R5
msync # Before writing to L1CSR0, execute msync & isync
isync
mtspr L1CSR0,r5 # Move R5 to the L1CSR0 (SPR 1010)register.
# This should start the CACHE lock Flash bit clear operation.
# this will take 134 cycles,
# Set up counter
lis r6, 0x0000 # Load counter value into R6
ori r6, r6, 0x0100
mtctr r6
waitCINVclear2:
bdnz waitCINVclear2 # wait for decrement counter
#****************************
# Confirm that cache invalidate operation is complete
li r6, 0x0002 # Set bit[30] in R6 (others are 0)
mfspr r5, L1CSR0 # Move L1CSR0 into R5
and r5, r5, r6 # Mask out all bits except CINV*
cmpli 0,r5,0x0002 # Compare if CINV, bit 30, = 1
# Set up counter
lis r6, 0x0000 # Load counter value into R6
ori r6, r6, 0x0100
mtctr r6
waitCINVclear3:
bdnz waitCINVclear3 # wait for decrement counter
#****************************
# Enable cache (totally unused/invalidated)
mfspr r5, L1CSR0 # Retrieve the L1CSR0 register value
oris r5, r5, CACHE_SETTINGS@h # OR in CWM and DPB in upper L1CSR0[11:12]
ori r5, r5, CACHE_SETTINGS@l # OR in cache enable bit L1CSR0[31]
msync # Before writing to L1CSR0, execute msync & isync
isync
mtspr L1CSR0, r5 # Return value to L1CSR0 to enable the cache
#****************************
# Now the Stack in Cache can be set up
# Load size of Cache to be used for Stack (4K)
lis r5, __STACK_SIZE@h # Stack size is 4KBytes
ori r5, r5, __STACK_SIZE@l
# Each stack lock instruction covers 32 bytes, so divide the input parameter
srwi r5, r5, 5 # Shift the contents of R5 right by 5 bits (size/32)
mtctr r5 # locations per cache line loaded to the CTR (SPR 9) register
# Point R5 to just past the system RAM (0x4001_0000). Set in the Linker file.
lis r5, __SP_END@h
ori r5, r5, __SP_END@l
# Run the loop to lock the cache lines for the stack
# The loop count is: 4KB / 32B = 128 = 0x80
_cache_loop:
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -