📄 mpc5500_asmcfg.s
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#**************************************************************************/
#* FILE NAME: mpc5500_asmcfg.s COPYRIGHT (c) Freescale 2004 */
#* All Rights Reserved */
#* DESCRIPTION: */
#* This file contains functions for the MPC5500 assembly configuration. */
#=========================================================================*/
#* */
#* REV AUTHOR DATE DESCRIPTION OF CHANGE */
#* --- ----------- ---------- --------------------- */
#* 0.1 G. Jackson 26/Mar/04 Initial version */
#* 0.2 G. Jackson 29/Apr/04 Made compiler names unique for */
#* assembly configuration. */
#* Single designation for rcw values. */
#* 0.3 G. Jackson 13/May/04 Changed definition of FMPLL_SYNCR */
#* register settings. */
#* 0.4 G. Jackson 15/May/04 Removed msync and isync from tlbwe */
#* commands. */
#* 0.5 G. Jackson 25/May/04 Changed __OPCOUNT to __SRAM_LOAD_SIZE */
#* Changed __SRAM_OPCODE to __SRAM_LOAD */
#* Changed cfg_OPCODE to cfg_SRAM_LOAD */
#* Changed OPCNT_OFFSET to IP_ADVANCE */
#* 0.6 G. Jackson 12/Jun/04 Changed TLB entries to work with */
#* MPC5554 Rev. 0.3 and later for the */
#* BAM, PBRIDGE_B, and Internal FLASH. */
#* 0.7 G. Jackson 30/Jun/04 Added entries for RCHW (RCHW_VAL) */
#* 0.8 G. Jackson 05/Aug/04 Added cfg_PNTRS for R13 and R2 */
#* 0.9 G. Jackson 18/Aug/04 Added cfg_ROMCPY for .data and .sdata */
#* 0.91 G. Jackson 20/Sep/04 cfg_ROMCPY changed to load by bytes. */
#* 0.92 G. Jackson 11/Oct/04 L1CSR0 checks added for complete */
#* cache operation. */
#* 1.0 G. Jackson 12/Oct/04 Green Hills now does not require */
#* quotation marks around the section */
#* Added syntax to generate symbols for */
#* debug. */
#* P&E See code comments for modifications */
#**************************************************************************/
.include "mpc5500_usrdefs.inc"
.include "flash_or_sram_run.inc"
.globl cfg_CACHE, cfg_FMPLL, cfg_SRAM, cfg_FLASH
.globl cfg_MMU, cfg_STACK, cfg_PNTRS, cfg_ROMCPY
.extern __start # Primary program entry point defined in __start.s
.extern __STACK_SIZE # Defined in the linker file
.extern __SP_INIT # Defined in the linker file
.extern __SP_END # Defined in the linker file
.extern __SRAM_LOAD # Defined in the linker file
.extern __SRAM_LOAD_SIZE # Defined in the linker file
.extern _SDA_BASE_ # Defined by the linker EABI
.extern _SDA2_BASE_ # Defined by the linker EABI
.extern cfg_SRAM_LOAD # Defined in mpc5500_SRAM_load.s
.extern __DATA_ROM # Defined in the linker file
# # Address of initialized data in Flash
.extern __ROM_COPY_SIZE # Defined in the linker file
# # Size of Flash area to be copied to SRAM
.extern __SRAM_CPY_START # Defined in the linker file
# # Address of ".data" section in SRAM
# set up separate section for the reset configuration half word and vector.
# This is the start of the .rcw section.
.if __PEGNU__
.section ".rcw","ax" # The "ax" is required to generate "non-text" code
.endif
.if __CWWRKS__ | __DIABCC__ | __GRNHS__
.section .rcw
.endif
.equ RCHW_VAL, (RCHW_WTE | RCHW_PS0 | BOOT_ID)
.if FLSH_RUN
.LONG RCHW_VAL
.LONG __start
.endif
# This is the end of the .rcw section.
#################################################
# This is the start of the .init section.
.if __PEGNU__
.section ".init","ax" # The "ax" is required to generate "non-text" code
.endif
.if __GRNHS__
.section .init,ax # The "ax" generates symbols for debug
.endif
.if __DIABCC__
.section .init,c # The "c" generates symbols for debug
.endif
.if __CWWRKS__
.section .init,text # The "text" generates symbols for debug
.endif
# Constants that should be defined follow:
# Defined assembler input parameters should allready understand:
# .equ MAS0,624
# .equ MAS1,625
# .equ MAS2,626
# .equ MAS3,627
# init_L2RAM requires the base address and the size of the SRAM.
# INT_SRAM_BASE, INT_SRAM_SIZE.
# Defined in linker file.
# Cache definitions:
# cfg_CACHE and init_STACK CACHE Settings
# __STACK_SIZE, __SP_INIT, __SP_END, (defined in linker file)
# .equ CACHE_CLEAR,(CLFC_NO_OP | CINV_INV_OP | CE_DISABLE)
# .equ CACHE_SETTINGS, (CWM_COPYBCK | DPB_NOPUSH | CE_ENABLE)
#***********************************************************************************/
# FUNCTION : cfg_mpc5500as */
# PURPOSE : This function provides an example for the overall */
# configuration for an mpc5500 device. */
# */
# In cases where (numerous) alternative initializations could */
# occur, a sample configuration is included here. Actual */
# initialization required for a specific system remains the */
# responsibility of the developer. */
# INPUT NOTES : None */
# RETURN NOTES : None */
# WARNING : None */
#***********************************************************************************/
# */
# MPC5500 initialization functions in order of call from __start.s */
#cfg_mpc5500as: */
# */
# The assembly actions are called in the order seen below. */
# They are called from __start in the file named __start.s */
# bl cfg_CACHE # Configure cache. */
# */
# bl cfg_FMPLL # Configure the Frequency Modulated Phase Locked Loop */
# */
# bl cfg_SRAM # Write to all SRAM locations for ECC functionality. */
# */
# bl cfg_FLASH # Reduce Wait States for Internal and External Flash */
# */
# bl cfg_MMU # Set up the TLB tables with the MMU registers. */
# */
# bl cfg_STACK # Set up the Stack in the Cache */
# */
# bl cfg_PNTRS # Set up the small data register pointers in R2 and R13 */
# */
# bl cfg_ROMCPY # Copy initialized data from FLASH ROM to SRAM */
# */
# blr # End of cfg_mpc5500as */
#***********************************************************************************/
#************************************************************************/
# CALLED SEQUENCES */
#************************************************************************/
#**************************************************************************/
# FUNCTION : cfg_CACHE */
# PURPOSE : This function initializes the CACHE by invalidating and */
# then enabling the cache. */
# INPUT NOTES : CACHE_CLEAR, CACHE_SETTINGS, L1CSR0 */
# RETURN NOTES : None */
# WARNING : Registers used: R5,R8,R9,R10 */
#**************************************************************************/
cfg_CACHE:
# To activate cache invalidate operation,
# place a "1" in the CINV bit location. (L1CSR0[30])
# This operation takes 134 cycles to complete
lis r5, CACHE_CLEAR@h # Load upper L1CSR0 (0x0) into R5
ori r5, r5, CACHE_CLEAR@l # Load lower L1CSR0 (CINV bit) into R5
mtspr L1CSR0,r5 # Move R5 to the L1CSR0 (SPR 1010)register.
# # This should start the CACHE invalidate
# # operation.
# Make sure that CINV is not active/finished
label_CINV_check: # Make sure that CINV is not active/finished
# The CINV mask bit will be compared to L1CSR0[30] CINV bit
lis r8, 0x0000 # Load upper CINV mask (0x0000) into R8
ori r8, r8, 0x0002 # Load lower L1CSR0[30] CINV mask bit into R8
#wait more than 176cycles to make sure the CINV bit is cleared
# Set up counter
lis r6, 0x0000 # Load counter value into R6
ori r6, r6, 0x0100
mtctr r6
waitCINVclear0:
bdnz waitCINVclear0 # wait for decrement counter
# Enable cache
mfspr r5, L1CSR0 # Retrieve the L1CSR0 register value
oris r5, r5, CACHE_SETTINGS@h # OR in CWM and DPB in upper L1CSR0[11:12]
ori r5, r5, CACHE_SETTINGS@l # OR in cache enable bit L1CSR0[31]
isync # Required before changing the CE bit to
msync # prevent disable/enable cache during access
mtspr L1CSR0, r5 # Return value to L1CSR0 to enable the cache
blr
# End of cfg_CACHE
#************************************************************************/
# FUNCTION : cfg_FMPLL */
# PURPOSE : This function configures the FMPLL. */
# INPUT NOTES : FMPLL_SYNCRREG, FMPLL_SYNSRREG, SIU_SRCRREG, */
# FMPLL_SYNCR_16_4, FMPLL_SYNCR_16_1, SIU_SRCR_SYSRST, */
# ERRLOGREG, ERRLOG_MFDERR, I_LOCEN, I_LOSSLRST, */
# I_LOSSCRST, I_LOCINT, I_LOLINT */
# RETURN NOTES : None */
# WARNING : Registers used: R5,R6,R8,R9,R10 */
# Alex modified @ 2007.03.28 Fix the latency
#************************************************************************/
cfg_FMPLL:
#*******************************************
# Set the internal clock to 32 MHz with MFD=16, and RFD=4.
# This sequence sets the MFD to 16 in the FMPLL_SYNCR Register.
lis r5, FMPLL_SYNCRREG@ha # Load address upper FMPLL_SYNCR into R5
addi r5, r5, FMPLL_SYNCRREG@l # Load address lower FMPLL_SYNCR into R5
# Load value upper FMPLL_SYNCR into R6
lis r6, FMPLL_SYNCR_SETTING1@h # Load value upper FMPLL_SYNCR into R6
ori r6, r6, FMPLL_SYNCR_SETTING1@l # Load value lower FMPLL_SYNCR into R6
stw r6, 0(r5) # Place value of R6 into FMPLL_SYNCR (address R5)
#*******************************************
# Check for loss-of-lock after MFD change
# Wait for PLL to lock. A timeout will occur after 6000 clocks.
# Set up counter
lis r6, 0x0000 # Load counter value into R6
ori r6, r6, 0x1770 # 6000 = 0x1770 for time out clocks
mtctr r6 # Move 0x1770 to the counter
# Load the lock bit mask into R8
lis r8, 0x0000 # Load LOCK mask value into R8
ori r8, r8, 0x0008 # LOCK bit is FMPLL_SYNSR[28]
# Load address of FMPLL_SYNSR
lis r6, FMPLL_SYNSRREG@h # Load address upper FMPLL_SYNSR into R6
ori r6, r6, FMPLL_SYNSRREG@l # Load address lower FMPLL_SYNSR into R6
PLLwaitLock:
bdnz PLLwaitLock # wait for decrement counter
# Check for lock achieved
lwz r9, 0(r6) # Load value of FMPLL_SYNSR into R9
and. r10, r9, r8 # AND FMPLL_SYNSR with the LOCK bit mask in R8
# # The "." after "and" activates the condition register
bne 0,PLLLocked # Branch not equal (not zero) (CR0[2] !=0)
#----------------------------------------
# Timeout has happened. Handle here
# Store MFD ERROR bit into the error log register
lis r9, ERRLOGREG@ha # Load upper address for error log into R9
ori r9, r9, ERRLOGREG@l # Load lower address for error log into R9
# Load MFD ERROR bit into error log (ERRLOG)
lis r10, ERRLOG_MFDERR@h # Load MFD ERROR bit into upper error log (ERRLOG)
ori r10, r10, ERRLOG_MFDERR@l # Load MFD ERROR bit into lower error log (ERRLOG)
stw r10, 0(r9) # Store error bit into the error log register
# Reset the part with a system reset
lis r9, SIU_SRCRREG@ha # Load upper address for SIU_SRCR into R9
addi r9, r9, SIU_SRCRREG@l # Load lower address for SIU_SRCR into R9
lis r10, SIU_SRCR_SYSRST@ha # Load Software system Reset (SSR bit)
addi r10, r10, SIU_SRCR_SYSRST@l # value into SIU_SRCR
stw r10, 0(r9) # Load SSR bit into SIU_SRCR[0]
# Device will enter system reset at this time
b FMPLL_RETURN # System reset is active, so this may never happen.
#----------------------------------------
# PLL is locked, continue
PLLLocked:
#***************************************
# Set the internal clock to 128 MHz with MFD=16, and RFD=1.
# This sequence sets the RFD to divide-by-1 in the FMPLL_SYNCR Register.
# R5 holds the FMPLL_SYNCR for this sequence.
lis r6, FMPLL_SYNCR_SETTING2@h # Load RFD value upper FMPLL_SYNCR into R6
ori r6, r6, FMPLL_SYNCR_SETTING2@l # Load value lower FMPLL_SYNCR into R6
stw r6, 0(r5) # Place value of R6 into FMPLL_SYNCR (address R5)
#**************************************
# The following "I_*" bits are set to one (or zeroed out) in mpc5500_usrdefs.inc
# R5 holds the FMPLL_SYNCR for these sequences
# Set loss of clock enable
# FMPLL.SYNCR.B.LOCEN = 1;
# Address for FMPLL_SYNCR is in R7
.if I_LOCEN # if .equ I_LOCEN = 1?
lwz r6,0(r5) # Load value of FMPLL_SYNCR into R6
oris r6,r6,0x0004 # Load the OR of LOCEN into R6
stw r6,0(r5) # Load into FMPLL_SYNCR
.endif
# Enable reset on loss of lock (Disable LOLIRQ)
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