mpc5500_usrdefs.inc

MPC5554处理器的初始化例程

    .long ( TLB_ENTRY_VALID | ENTRY_PROTECTED | GLOBAL_MATCH | TS_IS_COMPARE | TSIZ_64K )
# TLB3_MAS2
    .long ( SRAM_BASE_ADDR | CACHE_WRITE_BACK | CACHE_INHIBIT | MEM_NO_COHERENCE | PAGE_NOT_GUARDED | PAGE_BIG_ENDIAN )
# TLB3_MAS3
    .long ( SRAM_BASE_ADDR | READWRITEEXECUTE )

#** TLB entry 4 - PBRIDGE_A set to 1MB **
mmu_tlb4:
# TLB4_MAS0
    .long ( TLB_SELECT | TLB_ENTRY4 )
# TLB4_MAS1
    .long ( TLB_ENTRY_VALID | ENTRY_PROTECTED | GLOBAL_MATCH | TS_IS_COMPARE | TSIZ_1M )
# TLB4_MAS2
    .long ( PBRIDGEA_BASE_ADDR | CACHE_WRITE_BACK | CACHE_INHIBIT | MEM_NO_COHERENCE | PAGE_NOT_GUARDED | PAGE_BIG_ENDIAN )
# TLB4_MAS3
    .long ( PBRIDGEA_BASE_ADDR | READWRITEEXECUTE )

#** TLB entry 5 - Turn OFF TLB5 to eliminate duplication of Internal FLASH (1)
mmu_tlb5:
# TLB4_MAS0
    .long ( TLB_SELECT | TLB_ENTRY5 )
# TLB0_MAS1
    .long (TLB_ENTRY_INVALID | ENTRY_PROTECTED | GLOBAL_MATCH | TS_IS_COMPARE | TSIZ_1M )

#** TLB entry 6 - Internal FLASH (2) set to 256KB **
mmu_tlb6:
# TLB6_MAS0
    .long ( TLB_SELECT | TLB_ENTRY6 )
# TLB6_MAS1
    .long ( TLB_ENTRY_VALID | ENTRY_PROTECTED | GLOBAL_MATCH | TS_IS_COMPARE | TSIZ_256K )
# TLB6_MAS2
    .long ( (FLASH_BASE_ADDR + OFFSET_1M) | CACHE_WRITE_BACK | CACHE_ACTIVE | MEM_NO_COHERENCE | PAGE_NOT_GUARDED | PAGE_BIG_ENDIAN )
# TLB6_MAS3
    .long ( (FLASH_BASE_ADDR + OFFSET_1M) | READWRITEEXECUTE )

#** TLB entry 7 - Internal FLASH (3) set to 256KB **
mmu_tlb7:
# TLB7_MAS0
    .long ( TLB_SELECT | TLB_ENTRY7 )
# TLB7_MAS1
    .long ( TLB_ENTRY_VALID | ENTRY_PROTECTED | GLOBAL_MATCH | TS_IS_COMPARE | TSIZ_256K )
# TLB7_MAS2
    .long ( (FLASH_BASE_ADDR + OFFSET_1M + OFFSET_256K) | CACHE_WRITE_BACK | CACHE_ACTIVE | MEM_NO_COHERENCE | PAGE_NOT_GUARDED | PAGE_BIG_ENDIAN )
# TLB7_MAS3
    .long ( (FLASH_BASE_ADDR + OFFSET_1M + OFFSET_256K) | READWRITEEXECUTE )

#** TLB entry 8 - Internal FLASH (4) set to 256KB **
mmu_tlb8:
# TLB8_MAS0
    .long ( TLB_SELECT | TLB_ENTRY8 )
# TLB8_MAS1
    .long ( TLB_ENTRY_VALID | ENTRY_PROTECTED | GLOBAL_MATCH | TS_IS_COMPARE | TSIZ_256K )
# TLB8_MAS2
    .long ( (FLASH_BASE_ADDR + OFFSET_1M + OFFSET_512K) | CACHE_WRITE_BACK | CACHE_ACTIVE | MEM_NO_COHERENCE | PAGE_NOT_GUARDED | PAGE_BIG_ENDIAN )
# TLB8_MAS3
    .long ( (FLASH_BASE_ADDR + OFFSET_1M + OFFSET_512K) | READWRITEEXECUTE )

#** TLB entry 9 - Internal FLASH (5) set to 256KB **
mmu_tlb9:
# TLB9_MAS0
    .long ( TLB_SELECT | TLB_ENTRY9 )
# TLB9_MAS1
    .long ( TLB_ENTRY_VALID | ENTRY_PROTECTED | GLOBAL_MATCH | TS_IS_COMPARE | TSIZ_256K )
# TLB9_MAS2
    .long ( (FLASH_BASE_ADDR + OFFSET_1M + OFFSET_768K) | CACHE_WRITE_BACK | CACHE_ACTIVE | MEM_NO_COHERENCE | PAGE_NOT_GUARDED | PAGE_BIG_ENDIAN )
# TLB9_MAS3
    .long ( (FLASH_BASE_ADDR + OFFSET_1M + OFFSET_768K) | READWRITEEXECUTE )

#** TLB entry 10 - Cache used for Stack SRAM **
mmu_tlb10:
# TLB10_MAS0
    .long ( TLB_SELECT | TLB_ENTRY10 )
# TLB10_MAS1
    .long ( TLB_ENTRY_VALID | ENTRY_PROTECTED | GLOBAL_MATCH | TS_IS_COMPARE | TSIZ_4K )
# TLB10_MAS2
    .long ( (SRAM_BASE_ADDR + I_SRAM_SIZE) | CACHE_WRITE_BACK | CACHE_ACTIVE | MEM_NO_COHERENCE | PAGE_NOT_GUARDED | PAGE_BIG_ENDIAN )
# TLB10_MAS3
    .long ( (SRAM_BASE_ADDR + I_SRAM_SIZE) | READWRITEEXECUTE )

#** TLB entry 11 - External SRAM set to overall size of 4MB **
mmu_tlb11:
# TLB11_MAS0
    .long ( TLB_SELECT | TLB_ENTRY11 )
# TLB11_MAS1
    .long ( TLB_ENTRY_VALID | ENTRY_PROTECTED | GLOBAL_MATCH | TS_IS_COMPARE | TSIZ_4M )
# TLB11_MAS2
    .long ( (SRAM_BASE_ADDR - I_XSRAM_SPACE) | CACHE_WRITE_BACK | CACHE_INHIBIT | MEM_NO_COHERENCE | PAGE_NOT_GUARDED | PAGE_BIG_ENDIAN )
# TLB11_MAS3
    .long ( (SRAM_BASE_ADDR - I_XSRAM_SPACE) | READWRITEEXECUTE )

#** TLB entry 14 - Shadow Block set to overall size of 4K (Actual Shadow Block is 1K) **
mmu_tlb14:
# TLB14_MAS0
    .long ( TLB_SELECT | TLB_ENTRY14 )
# TLB14_MAS1
    .long ( TLB_ENTRY_VALID | ENTRY_PROTECTED | GLOBAL_MATCH | TS_IS_COMPARE | TSIZ_4K )
# TLB14_MAS2
    .long ( SHDW_BLK_ADDR | CACHE_WRITE_BACK | CACHE_ACTIVE | MEM_NO_COHERENCE | PAGE_NOT_GUARDED | PAGE_BIG_ENDIAN )
# TLB14_MAS3
    .long ( SHDW_BLK_ADDR | READWRITE )



#*********************************************************************/

  #P&E modification
  #Equates allow syntax that uses SPR name abreviations rather than register numbers
  .if __PEGNU__      
  /*.EQU bucsr,1013
    .EQU csrr0,58
    .EQU csrr1,59
    .EQU ctr,9
    .EQU dac1,316  
    .EQU dac2,317
    .EQU dbcnt,562
    .EQU dbcr0,308
    .EQU dbcr1,309
    .EQU dbcr2,310
    .EQU dbcr3,561
    .EQU dbsr,304
    .EQU dear,61  
    .EQU dec,22 
    .EQU decar,54
    .EQU dsrr0,574
    .EQU dsrr1,575
    .EQU esr,62
    .EQU hid0,1008
    .EQU hid1,1009
    .EQU iac1,312
    .EQU iac2,313
    .EQU iac3,314
    .EQU iac4,315
    .EQU ivor0,400
    .EQU ivor1,401
    .EQU ivor2,402  
    .EQU ivor3,403
    .EQU ivor4,404
    .EQU ivor5,405
    .EQU ivor6,406
    .EQU ivor7,407
    .EQU ivor8,408
    .EQU ivor9,409
    .EQU ivor10,410
    .EQU ivor11,411
    .EQU ivor12,412
    .EQU ivor13,413
    .EQU ivor14,414
    .EQU ivor15,415
    .EQU ivor32,528
    .EQU ivor33,529
    .EQU ivor34,530
    .EQU ivpr,63
    .EQU lr,8
    .EQU l1cfg0,515    
    .EQU l1csr0,1010 */
    .EQU L1CSR0,1010
  /*.EQU l1finv0,1016 */
    .EQU mas0,624
    .EQU mas1,625
    .EQU mas2,626
    .EQU mas3,627
  /*.EQU mas4,628
    .EQU mas6,630
    .EQU mcsr,572
    .EQU mmucfg,1015
    .EQU mmucsr0,1012
    .EQU pid0,48
    .EQU pir,286
    .EQU pvr,287
    .EQU spefscr,512
    .EQU sprg0,272
    .EQU sprg1,273
    .EQU sprg2,274
    .EQU sprg3,275
    .EQU sprg4,276
    .EQU sprg5,277
    .EQU sprg6,278
    .EQU sprg7,279
    .EQU srr0,26
    .EQU srr1,27
    .EQU svr,1023
    .EQU sprg4.r,260
    .EQU sprg5.r,261
    .EQU sprg6.r,262
    .EQU sprg7.r,263
    .EQU usprg0,256
    .EQU tbl,268 
    .EQU tbu,269
    .EQU tcr,340
    .EQU tlb0cfg,688
    .EQU tlb1cfg,689
    .EQU tsr,336
    .EQU xer,1
    .EQU tbl.s,284
    .EQU tbu.s,285 */    
  .endif