mpc5500_defs.inc

MPC5554处理器的初始化例程

#*************************************************************************
#* FILE NAME: mpc5500_defs.inc              COPYRIGHT (c) Freescale 2004 
#*                                                All Rights Reserved     
#* DESCRIPTION:                                                           
#* This file contains prototypes and definitions for the MPC5500 
#*  assembly functions.
#*
#*  Users should make no changes in this file. 
#*  User defines are in mpc5500_usrdefs.inc
#*========================================================================
#* ORIGINAL AUTHOR: G. Jackson           
#* REV      AUTHOR        DATE       DESCRIPTION OF CHANGE                
#* ---   -----------   -----------   ---------------------                  
#* 0.1   G. Jackson     26/Mar/04    Set up assembly definitions     
#* 0.2   G. Jackson     15/Apr/04    Add SRAM address definitions    
#* 0.3   G. Jackson     13/May/04    Removed 20MSB address definitions
#* 1.0   G. Jackson     25/May/04    Changed OPCNT_OFFSET to IP_ADVANCE
#* 1.1   R. Dees        25/May/04    Added more comments
#* 1.2   G. Jackson     30/Jun/04    Added RCHW constants
#*************************************************************************

#*************************************************************
#*************************************************************
# User should not modify any of the definitions below

#************************************************************************
#                            Definitions                                 
#************************************************************************

# Base addresses
    .equ FLASH_BASE_ADDR,     0x00000000
    .equ SRAM_BASE_ADDR,      0x40000000            ## INT_SRAM_BASE
    .equ INT_SRAM_SIZE,       0x00010000
    .equ INT_SRAM_128BYTSEGS, (INT_SRAM_SIZE >> 7)  ## Number of 128 byte segments
    .equ SHDW_BLK_ADDR,       0x00FFF000            ## Shadow Block starts at 0xFF_FC00 for 1K size
    .equ BAM_BASE_ADDR,       0x11300000
    .equ EXTMEM1_BASE_ADDR,   0x20000000
    .equ EXTMEM2_BASE_ADDR,   0x3FF80000

    .equ PBRIDGEA_BASE_ADDR,  0xC3F00000
    .equ EXTBUSINT_BASE_ADDR, 0xC3F84000
    .equ SIU_BASE_ADDR,       0xC3F90000
    .equ ETPU_BASE_ADDR,      0xC3FC0000

    .equ PBRIDGEB_BASE_ADDR,  0xFFF00000
    .equ XBAR_BASE_ADDR,      0xFFF04000
    .equ ECSM_BASE_ADDR,      0xFFF40000
    .equ EDMA_BASE_ADDR,      0xFFF44000
    .equ INTC_BASE_ADDR,      0xFFF48000
    .equ EQADC_BASE_ADDR,     0xFFF80000

# Size for defined address spaces
    .equ SIZE_4M,    0x00400000  #   4 MB
    .equ SIZE_1M,    0x00100000  #   1 MB
    .equ SIZE_768K,  0x000C0000  # 768 KB 
    .equ SIZE_512K,  0x00080000  # 512 KB 
    .equ SIZE_256K,  0x00040000  # 256 KB 
    .equ SIZE_64K,   0x00010000  #  64 KB 
    .equ SIZE_4K,    0x00001000  #   4 KB

#*************** Reset Configuration Half Word constants *********
    .equ WDOG_DISABLE, 0x00000000  # Watchdog is default disabled
    .equ WDOG_ENABLE,  0x04000000  # Watchdog is write once enabled
    .equ CS0_32BIT,    0x00000000  # CS0 external data bus is 32-bits
    .equ CS0_16BIT,    0x02000000  # CS0 external data bus is 16-bits
    .equ MPC5500_ID,   0x005A0000  # RCHW boot ID for MPC5500 devices

#*************** Cache initialization constants **************
# Definitions for the L1CSR0 (SPR1010) (L1 Cache control and Status Register 0)
# bit reference: L1CSR0((CWM<<20)|(DPB<<19)|(CLFC<<8)|(CINV<<1)|(CE)) 

# Fields used for L1CSR0 (L1 Cache Control and Status Register 0)
# CWM = Cache Write Mode = bit [11]
    .equ CWM_WRITE,   0x00000000  # 0x0
    .equ CWM_COPYBCK, 0x00100000  # 0x1
# DPB = Disable Push Buffer = bit [12]
    .equ DPB_PUSH,    0x00000000  # 0x0
    .equ DPB_NOPUSH,  0x00080000  # 0x1
# CLFC = Cache Lock Bits Flash Clear = bit [23]
    .equ CLFC_NO_OP,  0x00000000  # 0x0
    .equ CLFC_CLR_OP, 0x00000100  # 0x1
# CINV = Cache Invalidate = bit [30]
    .equ CINV_INV_OP, 0x00000002  # 0x1
    .equ CINV_NO_OP,  0x00000000  # 0x0
# CE = Cache Enable = bit [31]
    .equ CE_DISABLE,  0x00000000  # 0x0
    .equ CE_ENABLE,   0x00000001  # 0x1

#*************** FMPLL initialization constants **************
# Define the address for the FMPLL registers 
    .equ FMPLL_SYNCRREG, 0xC3F80000
    .equ FMPLL_SYNSRREG, 0xC3F80004
    .equ SIU_ECCRREG,    0xC3F90984
    .equ SIU_SRCRREG,    0xC3F90010

#*************************************************************
# Definitions for FMPLL_SYNCR (FMPLL Synthesizer Control Register) 
# bit reference: SYNCR((MFD<<23)|(RFD<<19)|(locen<<18)|
#                 (lolre<<17)|(locre<<16)|(disclk<<15)|(lolirq<<14)|
#                 (locirq<<13)|(rate<<12)|(depth<<10)|(exp))

# Fields used for PREDIV (Pre-Divider, bits [1:3]) 
    .equ PREDIV_1,  0x00000000  # 0x0
    .equ PREDIV_2,  0x10000000  # 0x1
    .equ PREDIV_3,  0x20000000  # 0x2
    .equ PREDIV_4,  0x30000000  # 0x3
    .equ PREDIV_5,  0x40000000  # 0x4

# Fields used for MFD (Muliplication Factor Divider, bits [4:8]) 
    .equ MFD_4,  0x00000000  # 0x0
    .equ MFD_6,  0x01000000  # 0x2
    .equ MFD_8,  0x02000000  # 0x4
    .equ MFD_10, 0x03000000  # 0x6
    .equ MFD_12, 0x04000000  # 0x8
    .equ MFD_14, 0x05000000  # 0xA
    .equ MFD_16, 0x06000000  # 0xC
    .equ MFD_18, 0x07000000  # 0xE

# Fields used for RFD (Reduced Frequency Divider, bits [10:12]) 
    .equ RFD_1,   0x00000000  # 0x0
    .equ RFD_2,   0x00080000  # 0x1
    .equ RFD_4,   0x00100000  # 0x2
    .equ RFD_8,   0x00180000  # 0x3
    .equ RFD_16,  0x00200000  # 0x4
    .equ RFD_32,  0x00280000  # 0x5
    .equ RFD_64,  0x00300000  # 0x6
    .equ RFD_128, 0x00380000  # 0x7

# Fields for LOCEN (Loss-of-clock enable, bit [13]) 
    .equ LOCEN_DIS, 0x00000000  # 0x0
    .equ LOCEN_EN,  0x00040000  # 0x1

# Fields for LOLRE (Loss-of-lock reset enable, bit [14]) 
    .equ LOLRE_IGNORE,   0x00000000  # 0x0
    .equ LOLRE_ASSERT,   0x00020000  # 0x1

# Fields for LOCRE (Loss-of-clock reset enable, bit [15]) 
    .equ LOCRE_IGNORE,   0x00000000  # 0x0
    .equ LOCRE_ASSERT,   0x00010000  # 0x1

# Fields for DISCLK (Disable CLKOUT, bit [16]) 
    .equ DISCLK_NORMAL, 0x00000000  # 0x0
    .equ DISCLK_LOW,    0x00008000  # 0x1

# Fields for LOLIRQ (Loss-of-lock interrupt request, bit [17]) 
    .equ LOLIRQ_NOT_REQUESTED, 0x00000000  # 0x0
    .equ LOLIRQ_REQUESTED,     0x00004000  # 0x1

# Fields for LOCIRQ (Loss-of-clock interrupt request, bit [18]) 
    .equ LOCIRQ_NOT_REQUESTED, 0x00000000  # 0x0
    .equ LOCIRQ_REQUESTED,     0x00002000  # 0x1

# Fields for RATE (Modulation rate, bit [19]) 
    .equ RATE_FREF_80, 0x00000000  # 0x0
    .equ RATE_FREF_40, 0x00001000  # 0x1

# Fields for DEPTH (Modulation depth percentage, bits [20:21])
    .equ DEPTH_0, 0x00000000  # 0x0
    .equ DEPTH_1, 0x00000400  # 0x1
    .equ DEPTH_2, 0x00000800  # 0x2

# Fields for EXP (Expected difference, bits [22:31])
    .equ EXP_0, 0x00000000  # 0x0

#*************************************************************
# Definitions for the FMPLL_SYNSR (Synthesizer Status Register) 
# bit reference: SYNSR ((lolf<<9)|(locf<<2))

# Fields for LOLF (Loss-of-lock flag, bit [22]) 
    .equ LOLF_NO_CHANGE, 0x00000000  # 0x0
    .equ LOLF_CLEAR,     0x00000200  # 0x1

# Fields for LOCF (Loss-of-clock flag, bit [29]) 
    .equ LOCF_NO_CHANGE, 0x00000000  # 0x0
    .equ LOCF_CLEAR,     0x00000004  # 0x1

#*************************************************************
# Definitions for the SIU_ECCR (External Clock Control Register) 
# bit reference: ECCR((ENGDIV<<8)|(EBTS<<3)|(EBDF)) 
    .equ ECCRREG, 0xC3F90984  # ECCR register address

# Fields for ENGDIV (Engineering clock values, bits [18:23]) 
    .equ ENGDIV_BY128, 0x00003F00  # 0x3F

# Fields for EBTS (external signals hold time, bit [28]) 
    .equ EBTS_NO_HOLD, 0x00000000  # 0x0
    .equ EBTS_HOLD,    0x00000004  # 0x1

# Fields for EBDF (CLKOUT divides, bits [30:31]) 
    .equ EBDF_DIVBY2, 0x00000001  # 0x1
    .equ EBDF_DIVBY4, 0x00000002  # 0x2

#*************************************************************
# Definitions for the SIU_SRCR (System Reset Control Register) 
# bit reference: SIU_SRCR ((SSR<<31)|(SER<<30)|(CRE<<15))

# Fields for SSR (software system reset, bit [0]) 
    .equ SSR_NORST,  0x00000000  # 0x0
    .equ SSR_SYSRST, 0x80000000  # 0x1

# Fields for SER (external system reset, bit [1]) 
    .equ SER_NORST, 0x00000000  # 0x0
    .equ SER_XRST,  0x40000000  # 0x1

# Fields for CRE (checkstop reset enable, bit [16]) 
    .equ CRE_NO, 0x00000000  # 0x0
    .equ CRE_EN, 0x00008000  # 0x1


#*************** Flash initialization constants ****************

# Definitions for FLASH_BIUCR (Flash BIU Control Register) 
# bit reference: FLSHBIUCR ((M3PFE<<19)|(M2PFE<<18)|
#               (M1PFE<<17)|(M0PFE<<16)|(APC<<13)|(WWSC<<11)|
#               (RWSC<<8)|(DPFEN<<6)|(IPFEN<<4)|(PFLIM<<1)|(BFEN))

# Fields for Flash Bus Interface Control 
# Fields for Prefetch Control (MnPFE Master n Prefetch Enable)
# Fields for M3PFE (Master 3 (EBI) prefetch enable, bit [12])
    .equ EBI_PREFTCH_OFF,  0x00000000  # 0x0
    .equ EBI_PREFTCH_ON,   0x00080000  # 0x1
# Fields for M2PFE (Master 2 (eDMA) prefetch enable, bit [13])
    .equ EDMA_PREFTCH_OFF, 0x00000000  # 0x0
    .equ EDMA_PREFTCH_ON,  0x00040000  # 0x1
# Fields for M1PFE (Master 1 (Nexus) prefetch enable, bit [14])
    .equ NEX_PREFTCH_OFF,  0x00000000  # 0x0
    .equ NEX_PREFTCH_ON,   0x00020000  # 0x1
# Fields for M0PFE (Master 0 (e200Z6 core) prefetch enable, bit [15])
    .equ CPU_PREFTCH_OFF,  0x00000000  # 0x0
    .equ CPU_PREFTCH_ON,   0x00010000  # 0x1

# Fields for APC (access pipelining control, bits [16:18]) 
    .equ APC_1,  0x00002000  # 0x1
    .equ APC_2,  0x00004000  # 0x2
    .equ APC_3,  0x00006000  # 0x3
    .equ APC_4,  0x00008000  # 0x4
    .equ APC_5,  0x0000A000  # 0x5
    .equ APC_6,  0x0000C000  # 0x6
    .equ APC_NO, 0x0000E000  # 0x7

# Fields for WWSC (write wait state control, bits [19:20]) 
    .equ WWSC_1, 0x00000800  # 0x1
    .equ WWSC_2, 0x00001000  # 0x2
    .equ WWSC_3, 0x00001800  # 0x3

# Fields for RWSC (read wait state control, bits [21:23]) 
    .equ RWSC_0, 0x00000000  # 0x0
    .equ RWSC_1, 0x00000100  # 0x1
    .equ RWSC_2, 0x00000200  # 0x2
    .equ RWSC_3, 0x00000300  # 0x3
    .equ RWSC_4, 0x00000400  # 0x4
    .equ RWSC_5, 0x00000500  # 0x5
    .equ RWSC_6, 0x00000600  # 0x6
    .equ RWSC_7, 0x00000700  # 0x7