mpc5500_ccdcfg.h

MPC5554处理器的初始化例程

#define AM_8M    0xFF800000 /* 0xFF800;   8M space */
#define AM_4M    0xFFC00000 /* 0xFFC00;   4M space */
#define AM_2M    0xFFE00000 /* 0xFFE00;   2M space */
#define AM_1M    0xFFF00000 /* 0xFFF00;   1M space */
#define AM_512K  0xFFF80000 /* 0xFFF80; 512K space */
#define AM_256K  0xFFFC0000 /* 0xFFFC0; 256K space */
#define AM_128K  0xFFFE0000 /* 0xFFFE0; 128K space */
#define AM_64K   0xFFFF0000 /* 0xFFFF0;  64K space */
#define AM_32K   0xFFFF8000 /* 0xFFFF8;  32K space */

/* Fields for the Cycle length (SCY) */
#define OR_SCY_0   0x00000000
#define OR_SCY_1   0x00000010
#define OR_SCY_2   0x00000020
#define OR_SCY_3   0x00000030
#define OR_SCY_4   0x00000040
#define OR_SCY_5   0x00000050
#define OR_SCY_6   0x00000060
#define OR_SCY_7   0x00000070
#define OR_SCY_8   0x00000080
#define OR_SCY_9   0x00000090
#define OR_SCY_10  0x000000A0
#define OR_SCY_11  0x000000B0
#define OR_SCY_12  0x000000C0
#define OR_SCY_13  0x000000D0
#define OR_SCY_14  0x000000E0
#define OR_SCY_15  0x000000F0

/* Fields for the Burst Cycle length (BSCY) */
#define OR_BSCY_0   0x00000000
#define OR_BSCY_1   0x00000002
#define OR_BSCY_2   0x00000004
#define OR_BSCY_3   0x00000006

/* Fields for Chip Selects */

#define CS_0  0
#define CS_1  1
#define CS_2  2
#define CS_3  3

/**************** PBRIDGE initialization constants *****************/

/* Definitions for PBRIDGE_A and PBRIDGE_B */

/* Fields for the Master Privilege Control Register (MPCR) */
#define MPCR_DEFAULT  0x77770000

/* Fields for the PACRx and OPACRx registers */
#define PACR_DEFAULT  0x44444444
#define OPACR_DEFAULT 0x44444444

/**************** XBAR initialization constants *****************/

/* Definitions for the XBAR */

/* Fields for the Master Priority registers (XBAR_MPRn) */
/*        where n = 0,1,3,6,7                           */
#define MPR_DEFAULT   0x00000210
#define MST2_PRI_HI   0x00000000
#define MST2_PRI_MED  0x00000100
#define MST2_PRI_LO   0x00000200
#define MST1_PRI_HI   0x00000000
#define MST1_PRI_MED  0x00000010
#define MST1_PRI_LO   0x00000020
#define MST0_PRI_HI   0x00000000
#define MST0_PRI_MED  0x00000001
#define MST0_PRI_LO   0x00000002

/* Fields for the Slave General Purpose Control register (XBAR_SGPCRn) */
/*        where n = 0,1,3,6,7                                          */
#define SGPCR_DEFAULT 0x00000000
#define RO_RW         0x00000000
#define RO_RO         0x80000000
#define ARB_FX        0x00000000
#define ARB_RROBIN    0x00000100
#define PCTL_PARKMST  0x00000000
#define PCTL_LASTMST  0x00000010
#define PCTL_NOMST    0x00000020
#define PARK_MSTPRT0  0x00000000
#define PARK_MSTPRT1  0x00000001
#define PARK_MSTPRT2  0x00000002

/* Fields used for all GPIO ports */
/* PA field - port assignment*/
#define GPIO_FUNCTION      0x0000
#define PRIMARY_FUNCTION   0x0C00
#define ALTERNATE_FUNCTION 0x0800

#define OUTPUT_BUFFER_ENABLE 0x0200
#define INPUT_BUFFER_ENABLE  0x0100
#define OUTPUT_MODE          0x0200
#define INPUT_MODE           0x0100
#define READBACK_ENABLE      0x0100

/* Fields used for Input */
#define ENABLE_HYSTERESIS  0x0010
#define DISABLE_HYSTERESIS 0x0000

/* treat WPE and WPS as 1 field for weak pull configuration */
#define WEAK_PULL_UP      0x0003
#define WEAK_PULL_DOWN    0x0002
#define WEAK_PULL_DISABLE 0x0000

/* Fields used for Output */
/* DSC field - drive strangth control */
#define DRIVE_STRENGTH_10PF 0x0000
#define DRIVE_STRENGTH_20PF 0x0040
#define DRIVE_STRENGTH_30PF 0x0080
#define DRIVE_STRENGTH_50PF 0x00C0

#define OUTPUT_DRAIN_ENABLE 0x0020
#define OUTPUT_DRAIN_DISABLE 0x0000

/* SRC field - slew rate control */
#define MINIMUM_SLEW_RATE 0x0000
#define MEDIUM_SLEW_RATE  0x0004
#define MAXIMUM_SLEW_RATE 0x000C



/**************************************************************************/
/*                                                                        */
/* Definition for needed Special Purpose registers                        */
/*                                                                        */
/*                                                                        */
/*  CPU Special Purpose Registers (SPR's) are defined in mpc5554_spr.h    */
/*                                                                        */
/**************************************************************************/
/*                       Function Prototypes                              */
/**************************************************************************/

/* Overall initialization function prototype */
void cfg_mpc5500ccd();

/**************************************************************************/
/*                       C Code Prototypes                                */
/**************************************************************************/

/* This function calls for configuration of the external clocks */
void cfg_XCLKS();

/* This function configures PBRIDGE_A and PBRIDGE_B    */
void cfg_PBRIDGE();

/* This function configures Slave ports and Master priorities */
/*     in the XBAR                                            */
void cfg_XBAR();


/**************************************************************************/
/*                       SIU Prototypes                                   */
/**************************************************************************/

/* This function initializes the EBI. */
void cfg_PCR();

/* This function configures the Pad Configuration Registers (PCR's) for ADDR[8:31] */
void cfg_PCR_ADDR(uint16_t PA_A, uint16_t OBE_A, uint16_t IBE_A, \
                 uint16_t DSC_A, uint16_t ODE_A, uint16_t HYS_A, \
                 uint16_t SRC_A, uint16_t WPE_A, uint16_t WPS_A);

/* This function configures the Pad Configuration Registers (PCR's) for DATA[0:15] */
/*                                                                 and DATA[16:31] */
void cfg_PCR_DATA(uint16_t PA_D, uint16_t OBE_D, uint16_t IBE_D, \
                 uint16_t DSC_D, uint16_t ODE_D, uint16_t HYS_D, \
                 uint16_t SRC_D, uint16_t WPE_D, uint16_t WPS_D, \
                 uint8_t DATA_BITS);

/* This function configures the Pad Configuration Registers (PCR's) for Control */
void cfg_PCR_CTRL(uint16_t PA_C, uint16_t OBE_C, uint16_t IBE_C, \
                 uint16_t DSC_C, uint16_t ODE_C, uint16_t HYS_C, \
                 uint16_t SRC_C, uint16_t WPE_C, uint16_t WPS_C, \
                 uint8_t FRST_PCR, uint8_t PCR_CNT);


/**************************************************************************/
/*                       EBI Prototypes                                   */
/**************************************************************************/

/* This function initializes the EBI. */
void cfg_EBI();

/* This function configures the EBI module before any chip select configuration */
void cfg_EBI_mod(uint32_t SIZEN_val, uint32_t SIZE_val, uint32_t ACGE_val, \
                 uint32_t EXTM_val, uint32_t EARB_val, uint32_t EARP_val, \
                 uint32_t MDIS_val, uint32_t DBM_val);

/* This function configures the base register for a certain chip select */
void cfg_CSn_BR(uint8_t CS_val, uint32_t BM_val, uint32_t PS_val, \
                         uint32_t BL_val, uint32_t WEBS_val, uint32_t TBDIP_val, \
                         uint32_t BI_val, uint32_t V_val);

/* This function configure the option register for a certain chip select */
void cfg_CSn_OR(uint8_t CS_val, uint32_t AM_val, uint32_t SCY_val, \
                         uint32_t BSCY_val);


#ifdef  __cplusplus
}
#endif