mpc5500_spr.h

MPC5554处理器的初始化例程

                vuint32_t FINVE:1;
                vuint32_t FDBZE:1;
                vuint32_t FUNFE:1;
                vuint32_t FOVFE:1;
                vuint32_t FRMC:2;
            } B;
        };

/****************************************************************************/
/*                   CPU REGISTERS: Exception Handling/Control Registers    */
/****************************************************************************/
        union SPR_SPRGVAL { /* There are [8] entries for this tag */
            vuint32_t R;
            struct {
                vuint32_t SPRDATA:32;
            } B;
        };

        union SPR_USPRG0VAL {
            vuint32_t R;
            struct {
                vuint32_t USPR0DATA:32;
            } B;
        };

       union SPR_SRR0VAL {
            vuint32_t R;
            struct {
                vuint32_t NXTADDR:32;
            } B;
        };

       union SPR_SRR1VAL {
            vuint32_t R;
            struct {
                vuint32_t MSRSTATE:32;
            } B;
        };

        union SPR_CSRR0VAL {
            vuint32_t R;
            struct {
                vuint32_t CRITNXTADDR:32;
            } B;
        };

       union SPR_CSRR1VAL {
            vuint32_t R;
            struct {
                vuint32_t CRITMSRSTATE:32;
            } B;
        };

        union SPR_DSRR0VAL {
            vuint32_t R;
            struct {
                vuint32_t DBGNXTADDR:32;
            } B;
        };

       union SPR_DSRR1VAL {
            vuint32_t R;
            struct {
                vuint32_t DBGMSRSTATE:32;
            } B;
        };

       union SPR_DEARVAL {
            vuint32_t R;
            struct {
                vuint32_t DATEFADDR:16;
                vuint32_t :16;
            } B;
        };

        union SPR_ESRVAL {
            vuint32_t R;
            struct {
                vuint32_t :4;
                vuint32_t PIL:1;
                vuint32_t PPR:1;
                vuint32_t PTR:1;
                vuint32_t FP:1;
                vuint32_t ST:1;
                vuint32_t :1;
                vuint32_t DLK:1;
                vuint32_t ILK:1;
                vuint32_t AP:1;
                vuint32_t PUO:1;
                vuint32_t BO:1;
                vuint32_t PIE:1;
                vuint32_t :8;
                vuint32_t SPE:1;
                vuint32_t :6;
                vuint32_t XTE:1;
            } B;
        };


        union SPR_MCSRVAL {
            vuint32_t R;
            struct {
                vuint32_t MCP:1;
                vuint32_t :1;
                vuint32_t CP_PERR:1;
                vuint32_t CPERR:1;
                vuint32_t EXCP_ERR:1;
                vuint32_t :24;
                vuint32_t BUS_WRERR:1;
                vuint32_t :2;
            } B;
        };

       union SPR_IVPRVAL {
            vuint32_t R;
            struct {
                vuint32_t VECBASE:16;
                vuint32_t :16;
            } B;
        };

 /* Note: IVOR0 is not supported by the MPC5554 */
        union SPR_IVORVAL {  /* There are [16] entries for this tag */
            vuint32_t R;
            struct {
                vuint32_t :16;
                vuint32_t VECOFFSET:12;
                vuint32_t :4;
            } B;
        };

        union SPR_IVOR32VAL {
            vuint32_t R;
            struct {
                vuint32_t :16;
                vuint32_t VECOFFSET:12;
                vuint32_t :4;
            } B;
        };

        union SPR_IVOR33VAL {
            vuint32_t R;
            struct {
                vuint32_t :16;
                vuint32_t VECOFFSET:12;
                vuint32_t :4;
            } B;
        };

        union SPR_IVOR34VAL {
            vuint32_t R;
            struct {
                vuint32_t :16;
                vuint32_t VECOFFSET:12;
                vuint32_t :4;
            } B;
        };

/****************************************************************************/
/*                   CPU REGISTERS: DEBUG                                     */
/****************************************************************************/
        union {
            vuint32_t R;
            struct SPR_DBCR0VAL {
                vuint32_t EDM:1;
                vuint32_t IDM:1;
                vuint32_t RST:2;
                vuint32_t ICMP:1;
                vuint32_t BRT:1;
                vuint32_t IRPT:1;
                vuint32_t TRAP:1;
                vuint32_t IAC1:1;
                vuint32_t IAC2:1;
                vuint32_t IAC3:1;
                vuint32_t IAC4:1;
                vuint32_t DAC1:2;
                vuint32_t DAC2:2;
                vuint32_t RET:1;
                vuint32_t :4;
                vuint32_t DEVT1:1;
                vuint32_t DEVT2:1;
                vuint32_t DCNT1:1;
                vuint32_t DCNT2:1;
                vuint32_t CIRPT:1;
                vuint32_t CRET:1;
                vuint32_t :4;
                vuint32_t FT:1;
            } B;
        };

        union SPR_DBCR1VAL {
            vuint32_t R;
            struct {
                vuint32_t IAC1US:2;
                vuint32_t IAC1ER:2;
                vuint32_t IAC2US:2;
                vuint32_t IAC2ER:2;
                vuint32_t IAC12M:2;
                vuint32_t :6;
                vuint32_t IAC3US:2;
                vuint32_t IAC3ER:2;
                vuint32_t IAC4US:2;
                vuint32_t IAC4ER:2;
                vuint32_t IAC34M:2;
                vuint32_t :6;
            } B;
        };

        union SPR_DBCR2VAL {
            vuint32_t R;
            struct {
                vuint32_t DIAC1US:2;
                vuint32_t DIAC1ER:2;
                vuint32_t DIAC2US:2;
                vuint32_t DIAC2ER:2;
                vuint32_t DIAC12M:2;
                vuint32_t DAC1LNK:2;
                vuint32_t DAC2LNK:2;
                vuint32_t :20;
            } B;
        };

         union SPR_DBCR3VAL {
            vuint32_t R;
            struct {
                vuint32_t DEVT1C1:1;
                vuint32_t DEVT2C1:1;
                vuint32_t ICMPC1:1;
                vuint32_t IAC1C1:1;
                vuint32_t IAC2C1:1;
                vuint32_t IAC3C1:1;
                vuint32_t IAC4C1:1;
                vuint32_t DAC1RC1:1;
                vuint32_t DAC1WC1:1;
                vuint32_t DAC2RC1:1;
                vuint32_t DAC2WC1:1;
                vuint32_t IRPTC1:1;
                vuint32_t RETC1:1;
                vuint32_t DEVT1C2:1;
                vuint32_t DEVT2C2:1;
                vuint32_t ICMPC2:1;
                vuint32_t IAC1C2:1;
                vuint32_t IAC2C2:1;
                vuint32_t IAC3C2:1;
                vuint32_t IAC4C2:1;
                vuint32_t DAC1RC2:1;
                vuint32_t DAC1WC2:1;
                vuint32_t DAC2RC2:1;
                vuint32_t DAC2WC2:1;
                vuint32_t DEVT1T1:1;
                vuint32_t DEVT2T1:1;
                vuint32_t IAC1T1:1;
                vuint32_t IAC3T1:1;
                vuint32_t DAC1RT1:1;
                vuint32_t DAC1WT1:1;
                vuint32_t CNT2T1:1;
                vuint32_t CONFIG:1;
            } B;
        };

        union SPR_DBSRVAL {
            vuint32_t R;
            struct {
                vuint32_t IDE:1;
                vuint32_t UDE:1;
                vuint32_t MRR:2;
                vuint32_t ICMP:1;
                vuint32_t BRT:1;
                vuint32_t IRPT:1;
                vuint32_t TRAP:1;
                vuint32_t IAC1:1;
                vuint32_t IAC2:1;
                vuint32_t IAC3:1;
                vuint32_t IAC4:1;
                vuint32_t DAC1R:1;
                vuint32_t DAC1W:1;
                vuint32_t DAC2R:1;
                vuint32_t DAC2W:1;
                vuint32_t RET:1;
                vuint32_t :4;
                vuint32_t DEVT1:1;
                vuint32_t DEVT2:1;
                vuint32_t DCNT1:1;
                vuint32_t DCNT2:1;
                vuint32_t CIRPT:1;
                vuint32_t CRET:1;
                vuint32_t :4;
                vuint32_t CNT1RG:1;
            } B;
        };

        union SPR_DBCNTVAL {
            vuint32_t R;
            struct {
                vuint32_t CNT1:16;
                vuint32_t CNT2:16;
           } B;
        };

        union SPR_IAC1VAL {
            vuint32_t R;
            struct {
                vuint32_t INSTADDR:30;
                vuint32_t :2;
           } B;
        };

        union SPR_IAC2VAL {
            vuint32_t R;
            struct {
                vuint32_t INSTADDR:30;
                vuint32_t :2;
           } B;
        };

        union SPR_IAC3VAL {
            vuint32_t R;
            struct {
                vuint32_t INSTADDR:30;
                vuint32_t :2;
           } B;
        };

        union SPR_IAC4VAL {
            vuint32_t R;
            struct {
                vuint32_t INSTADDR:30;
                vuint32_t :2;
           } B;
        };


        union SPR_DAC1VAL {
            vuint32_t R;
            struct {
                vuint32_t DATTADDR:32;
           } B;
        };

        union SPR_DAC2VAL {
            vuint32_t R;
            struct {
                vuint32_t DATTADDR:32;
           } B;
        };



/*****************************************************/
/* Define instances of modules                       */
/*  with special register numbers                    */
/*****************************************************/

// The CR register does not have an SPR#
// The GPR registers do not have an SPR#
// The MSR register does not have an SPR#

#define SPR_LR          8
#define SPR_CTR         9
#define SPR_XER         1

#define SPR_PIR       286
#define SPR_PVR       287
#define SPR_SVR      1023
#define SPR_HID0     1008
#define SPR_HID1     1009

#define SPR_TBL       284
#define SPR_TBU       285
#define SPR_TCR       340
#define SPR_TSR       336
#define SPR_DEC        22
#define SPR_DECAR      54

#define SPR_PID0       48
#define SPR_MMUCSR0  1012
#define SPR_MMUCFG   1015
#define SPR_TLB0CFG   688
#define SPR_TLB1CFG   689
#define SPR_MAS0      624
#define SPR_MAS1      625
#define SPR_MAS2      626
#define SPR_MAS3      627
#define SPR_MAS4      628
#define SPR_MAS6      630

#define SPR_L1CFG0    515
#define SPR_L1CSR0   1010
#define SPR_L1FINV0  1016

#define SPR_SPEFSCR   512

#define SPR_SPRG0     272
#define SPR_SPRG1     273
#define SPR_SPRG2     274
#define SPR_SPRG3     275
#define SPR_SPRG4     276
#define SPR_SPRG5     277
#define SPR_SPRG6     278
#define SPR_SPRG7     279
#define SPR_USPRG0    256
#define SPR_SRR0       26
#define SPR_SRR1       27
#define SPR_CSRR0      58
#define SPR_CSRR1      59
#define SPR_DSRR0     574
#define SPR_DSRR1     575
#define SPR_ESR        62
#define SPR_MCSR      572
#define SPR_DEAR       61
#define SPR_IVPR       63
#define SPR_IVOR0     400
#define SPR_IVOR1     401
#define SPR_IVOR2     402
#define SPR_IVOR3     403
#define SPR_IVOR4     404
#define SPR_IVOR5     405
#define SPR_IVOR6     406
#define SPR_IVOR7     407
#define SPR_IVOR8     408
#define SPR_IVOR9     409
#define SPR_IVOR10    410
#define SPR_IVOR11    411
#define SPR_IVOR12    412
#define SPR_IVOR13    413
#define SPR_IVOR14    414
#define SPR_IVOR15    415
#define SPR_IVOR32    528
#define SPR_IVOR33    529
#define SPR_IVOR34    530

#define SPR_DBCR0     308
#define SPR_DBCR1     309
#define SPR_DBCR2     310
#define SPR_DBCR3     561
#define SPR_DBSR      304
#define SPR_DBCNT     562
#define SPR_IAC1      312
#define SPR_IAC2      313
#define SPR_IAC3      314
#define SPR_IAC4      315
#define SPR_DAC1      316
#define SPR_DAC2      317



#ifdef  __cplusplus
}
#endif

#endif  /* ends inclusion of #ifndef __MPC5500_SPR_ for one instantiation */

/*********************************************************************
 *
 * Copyright:
 *	Freescale Semiconductor, INC. All Rights Reserved.
 *  You are hereby granted a copyright license to use, modify, and
 *  distribute the SOFTWARE so long as this entire notice is
 *  retained without alteration in any modified and/or redistributed
 *  versions, and that such modified versions are clearly identified
 *  as such. No licenses are granted by implication, estoppel or
 *  otherwise under any patents or trademarks of Freescale
 *  Semiconductor, Inc. This software is provided on an "AS IS"
 *  basis and without warranty.
 *
 *  To the maximum extent permitted by applicable law, Freescale
 *  Semiconductor DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
 *  INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A
 *  PARTICULAR PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH
 *  REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF)
 *  AND ANY ACCOMPANYING WRITTEN MATERIALS.
 *
 *  To the maximum extent permitted by applicable law, IN NO EVENT
 *  SHALL Freescale Semiconductor BE LIABLE FOR ANY DAMAGES WHATSOEVER
 *  (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS,
 *  BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER
 *  PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.
 *
 *  Freescale Semiconductor assumes no responsibility for the
 *  maintenance and support of this software
 *
 ********************************************************************/