📄 mpc5500_spr.h
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/**************************************************************************
* FILE NAME: $RCSfile: mpc5500_spr.h,v $ COPYRIGHT (c) Freescale 2005 *
* DESCRIPTION: All Rights Reserved *
* This file contain all of the SPR register and bit field definitions *
* for MPC5500 products. There are no address assignments for the SPR *
* registers. Instead, the bit field structures are only assigned. *
* SPR register numbers are also assigned. *
*========================================================================*
* ORIGINAL AUTHOR: Glenn Jackson *
* $Log: mpc5500_spr.h,v $
* Revision 1.3 2005/02/22 13:49:32 r47354
* Made the same as file currently on extranet.
* Changed _MPC5554_SPR_ to _MPC5500_SPR_.
* Changed to Freescale copyrigh/discimer.
*
* Revision 1.2 2005/02/22 13:06:16 r47354
* Prepend all Special Purpose Register names with "SPR_" to prevent issues when using this file with mpc5553/4.h
*
* Revision 1.1 2005/02/22 10:55:20 r47354
* Initial revision. Based on mpc5554_spr.h
*........................................................................*
* 0.01 G. Jackson 13/Nov/03 Initial version of file for SPR *
* registers in the MPC5554. *
* Based on SoC version 0.7. *
* 1.0 G. Jackson 23/Jan/04 Replaced MASnVAL with MASnCVAL to *
* maintain unique function defintions. *
* 1.1 G. Jackson 19/Jul/04 #endif note placed after _MPC5554_SPR_ *
* #ifndef and #define. *
* Changed structures to typedefs that *
* would be instantiated by customer *
* definition later in code. *
* 1.2 G.Jackson 14/Sep/04 Added SPR_ prefixes for unique names. *
**************************************************************************/
/* >>>>NOTE! this file describes fixed special purpose registers. */
/* Please do not edit it directly!<<<< */
#ifndef _MPC5500_SPR_
#define _MPC5500_SPR_
/* This ifndef has a corresponding #endif at the bottom of this file */
/* so that it will only be included once. */
#include "typedefs.h"
#ifdef __cplusplus
extern "C" {
#endif
/********************************************/
/* Example instantiation and use: */
/* union CRVAL my_cr; */
/* my_cr.B.CR0 = 1; */
/* my_cr.R = 0x10000000 */
/********************************************/
/****************************************************************************/
/* CPU REGISTERS: General Registers */
/****************************************************************************/
union SPR_CRVAL {
vuint32_t R;
struct {
vuint32_t CR0:4;
vuint32_t CR1:4;
vuint32_t CR2:4;
vuint32_t CR3:4;
vuint32_t CR4:4;
vuint32_t CR5:4;
vuint32_t CR6:4;
vuint32_t CR7:4;
} B;
};
union SPR_LRVAL {
vuint32_t R;
struct {
vuint32_t LINKADDRESS:32;
} B;
};
union SPR_CTRVAL {
vuint32_t R;
struct {
vuint32_t COUNTVALUE:32;
} B;
};
union SPR_XERVAL {
vuint32_t R;
struct {
vuint32_t SO:1;
vuint32_t OV:1;
vuint32_t CA:1;
vuint32_t :22;
vuint32_t BYTECNT:7;
} B;
};
/****************************************************************************/
/* CPU REGISTERS: Processor Control Registers */
/****************************************************************************/
union SPR_MSRVAL {
vuint32_t R;
struct {
vuint32_t :5;
vuint32_t UCLE:1;
vuint32_t SPE:1;
vuint32_t :6;
vuint32_t WE:1;
vuint32_t CE:1;
vuint32_t :1;
vuint32_t EE:1;
vuint32_t PR:1;
vuint32_t FP:1;
vuint32_t ME:1;
vuint32_t FE0:1;
vuint32_t :1;
vuint32_t DE:1;
vuint32_t FE1:1;
vuint32_t :2;
vuint32_t IS:1;
vuint32_t DS:1;
vuint32_t :4;
} B;
};
union SPR_PIRVAL {
vuint32_t R;
struct {
vuint32_t :24;
vuint32_t ID:8;
} B;
};
union SPR_PVRVAL {
vuint32_t R;
struct {
vuint32_t MFGID:4;
vuint32_t :2;
vuint32_t TYPE:6;
vuint32_t VER:4;
vuint32_t MGBUSE:8;
vuint32_t MJRREV:4;
vuint32_t MGBID:4;
} B;
};
union SPR_SVRVAL {
vuint32_t R;
struct {
vuint32_t SYSVER:32;
} B;
};
union SPR_HID0VAL {
vuint32_t R;
struct {
vuint32_t EMCP:1;
vuint32_t :5;
vuint32_t BPRED:2;
vuint32_t DOZE:1;
vuint32_t NAP:1;
vuint32_t SLEEP:1;
vuint32_t :3;
vuint32_t ICR:1;
vuint32_t NHR:1;
vuint32_t :1;
vuint32_t TBEN:1;
vuint32_t SEL_TBCLK:1;
vuint32_t DCLREE:1;
vuint32_t DCLRCE:1;
vuint32_t CICLRDE:1;
vuint32_t MCCLRDE:1;
vuint32_t DAPUEN:1;
vuint32_t :8;
} B;
};
union SPR_HID1VAL {
vuint32_t R;
struct {
vuint32_t :24;
vuint32_t ATS:1;
vuint32_t :7;
} B;
};
/****************************************************************************/
/* CPU REGISTERS: TIMERS */
/****************************************************************************/
union SPR_TBLVAL {
vuint32_t R;
struct {
vuint32_t TBLVALUE:32;
} B;
};
union SPR_TBUVAL {
vuint32_t R;
struct {
vuint32_t TBUVALUE:32;
} B;
};
union SPR_TCRVAL {
vuint32_t R;
struct {
vuint32_t WP:2;
vuint32_t WRC:2;
vuint32_t WIE:1;
vuint32_t DIE:1;
vuint32_t FP:2;
vuint32_t FIE:1;
vuint32_t ARE:1;
vuint32_t :1;
vuint32_t WPEXT:4;
vuint32_t FPEXT:4;
vuint32_t :13;
} B;
};
union SPR_TSRVAL {
vuint32_t R;
struct {
vuint32_t ENW:1;
vuint32_t WIS:1;
vuint32_t WRS:2;
vuint32_t DIS:1;
vuint32_t FIS:1;
vuint32_t :26;
} B;
};
union SPR_DECVAL {
vuint32_t R;
struct {
vuint32_t DECVALUE:32;
} B;
};
union SPR_DECARVAL {
vuint32_t R;
struct {
vuint32_t DECARVALUE:32;
} B;
};
/****************************************************************************/
/* CPU REGISTERS: MMU */
/****************************************************************************/
union SPR_PID0VAL {
vuint32_t R;
struct {
vuint32_t :24;
vuint32_t PID:8;
} B;
};
union SPR_MMUCSR0VAL {
vuint32_t R;
struct {
vuint32_t :30;
vuint32_t TLBCAM_FI:1;
vuint32_t:1;
} B;
};
union SPR_MMUCFGVAL {
vuint32_t R;
struct {
vuint32_t:17;
vuint32_t NPIDS:4;
vuint32_t PIDSIZE:5;
vuint32_t:2;
vuint32_t NLTBS:2;
vuint32_t MAVN:2;
} B;
};
union SPR_TLB0CFGVAL {
vuint32_t R;
struct {
vuint32_t ASSOC:8;
vuint32_t MINSIZE:4;
vuint32_t MAXSIZE:4;
vuint32_t IPROT:1;
vuint32_t AVAIL:1;
vuint32_t :2;
vuint32_t NENTRY:12;
} B;
};
union SPR_TLB1CFGVAL {
vuint32_t R;
struct {
vuint32_t ASSOC:8;
vuint32_t MINSIZE:4;
vuint32_t MAXSIZE:4;
vuint32_t IPROT:1;
vuint32_t AVAIL:1;
vuint32_t :2;
vuint32_t NENTRY:12;
} B;
};
union SPR_MAS0CVAL {
vuint32_t R;
struct {
vuint32_t:2;
vuint32_t TLBSEL:2;
vuint32_t:7;
vuint32_t ESELCAM:5;
vuint32_t:11;
vuint32_t NVCAM:5;
} B;
};
union SPR_MAS1CVAL {
vuint32_t R;
struct {
vuint32_t VALID:1;
vuint32_t IPROT:1;
vuint32_t:6;
vuint32_t TID:8;
vuint32_t:3;
vuint32_t TS:1;
vuint32_t TSIZ:4;
vuint32_t:8;
} B;
};
union SPR_MAS2CVAL {
vuint32_t R;
struct {
vuint32_t EPN:20; /* Effective Page Number */
vuint32_t:7;
vuint32_t W:1; /* Write through required; */
/* 0=write back; 1=write through */
vuint32_t I:1; /* Cache Inhibit; 0=not inhibited */
vuint32_t M:1; /* Memory coherence; 0=not required */
vuint32_t G:1; /* Gaurded; 0=not gaurded */
vuint32_t E:1; /* Endianess; 0=Big; 1=Little */
} B;
};
union SPR_MAS3CVAL {
vuint32_t R;
struct {
vuint32_t RPN:20; /* Real Page Number */
vuint32_t:2;
vuint32_t U0:1; /* User bits [0:3] */
vuint32_t U1:1;
vuint32_t U2:1;
vuint32_t U3:1;
vuint32_t UX:1; /* Permission bits */
vuint32_t SX:1;
vuint32_t UW:1;
vuint32_t SW:1;
vuint32_t UR:1;
vuint32_t SR:1;
} B;
};
union SPR_MAS4CVAL {
vuint32_t R;
struct {
vuint32_t:2;
vuint32_t TLBSELD:2;
vuint32_t:10;
vuint32_t TIDSELD:2;
vuint32_t:4;
vuint32_t TSIZED:4;
vuint32_t :3;
vuint32_t WD:1;
vuint32_t ID:1;
vuint32_t MD:1;
vuint32_t GD:1;
vuint32_t ED:1;
} B;
};
union SPR_MAS6CVAL {
vuint32_t R;
struct {
vuint32_t:8;
vuint32_t SPID:8;
vuint32_t:15;
vuint32_t SAS:1;
} B;
};
/****************************************************************************/
/* CPU REGISTERS: CACHE */
/****************************************************************************/
union SPR_L1CFG0VAL { /* Read only register */
vuint32_t R;
struct {
vuint32_t CARCH:2; /* Cache Architecture; 01=Unified */
vuint32_t CWPA:1; /* Cache way partitioning available =1 */
vuint32_t CFAHA:1; /* Cache Flush by all avail; 0=not */
vuint32_t CFISWA:1; /* Cache Flush Inv by set & way avail=1 */
vuint32_t :2;
vuint32_t CBSIZE:2; /* Block Size 00=32 bytes */
vuint32_t CREPL:2; /* Replacement Policy 10=pseudo round robin */
vuint32_t CLA:1; /* Line locking APU; 1=avail */
vuint32_t CPA:1; /* Parity available 1=avail */
vuint32_t CNWAY:8; /* Num of ways; 0x03=4way, 0x07=8way */
vuint32_t CSIZE:11; /* Size; 0x008=8KB, 0x010=16KB,0x020=32KB */
} B;
}; /* Read only register */
union SPR_L1CSR0VAL {
vuint32_t R;
struct {
vuint32_t WID:4;
vuint32_t WDD:4;
vuint32_t AWD:1;
vuint32_t AWDD:1;
vuint32_t :1;
vuint32_t CWM:1;
vuint32_t DPP:1;
vuint32_t DSB:1;
vuint32_t DSTR:1;
vuint32_t CPE:1;
vuint32_t :5;
vuint32_t CUL:1;
vuint32_t CLO:1;
vuint32_t CLFC:1;
vuint32_t :5;
vuint32_t CABT:1;
vuint32_t CINV:1;
vuint32_t CE:1;
} B;
};
union SPR_L1FINV0VAL {
vuint32_t R;
struct {
vuint32_t :5;
vuint32_t CWAY:3;
vuint32_t :12;
vuint32_t CSET:7;
vuint32_t :3;
vuint32_t CCMD:2;
} B;
};
/****************************************************************************/
/* CPU REGISTERS: APU */
/****************************************************************************/
union SPR_SPEFSCRVAL { /* Status and Control of SPE instructions */
vuint32_t R;
struct {
vuint32_t SOVH:1;
vuint32_t OVH:1;
vuint32_t FGH:1;
vuint32_t FXH:1;
vuint32_t FINVH:1;
vuint32_t FDBZH:1;
vuint32_t FUNFH:1;
vuint32_t FOVFH:1;
vuint32_t :2;
vuint32_t FINXS:1;
vuint32_t FINVS:1;
vuint32_t FDBZS:1;
vuint32_t FUNFS:1;
vuint32_t FOVFS:1;
vuint32_t MODE:1;
vuint32_t SOV:1;
vuint32_t OV:1;
vuint32_t FG:1;
vuint32_t FX:1;
vuint32_t FINV:1;
vuint32_t FDBZ:1;
vuint32_t FUNF:1;
vuint32_t FOVF:1;
vuint32_t :1;
vuint32_t FINXE:1;
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