📄 mpc5554.h
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vuint32_t:6;
vuint32_t SRV:4;
vuint32_t GPRE:8;
vuint32_t:8;
} B;
} MCR; /* Module Configuration Register */
union {
vuint32_t R;
struct {
vuint32_t:8;
vuint32_t F23:1;
vuint32_t F22:1;
vuint32_t F21:1;
vuint32_t F20:1;
vuint32_t F19:1;
vuint32_t F18:1;
vuint32_t F17:1;
vuint32_t F16:1;
vuint32_t F15:1;
vuint32_t F14:1;
vuint32_t F13:1;
vuint32_t F12:1;
vuint32_t F11:1;
vuint32_t F10:1;
vuint32_t F9:1;
vuint32_t F8:1;
vuint32_t F7:1;
vuint32_t F6:1;
vuint32_t F5:1;
vuint32_t F4:1;
vuint32_t F3:1;
vuint32_t F2:1;
vuint32_t F1:1;
vuint32_t F0:1;
} B;
} GFR; /* Global FLAG Register */
union {
vuint32_t R;
struct {
vuint32_t:8;
vuint32_t OU23:1;
vuint32_t OU22:1;
vuint32_t OU21:1;
vuint32_t OU20:1;
vuint32_t OU19:1;
vuint32_t OU18:1;
vuint32_t OU17:1;
vuint32_t OU16:1;
vuint32_t OU15:1;
vuint32_t OU14:1;
vuint32_t OU13:1;
vuint32_t OU12:1;
vuint32_t OU11:1;
vuint32_t OU10:1;
vuint32_t OU9:1;
vuint32_t OU8:1;
vuint32_t OU7:1;
vuint32_t OU6:1;
vuint32_t OU5:1;
vuint32_t OU4:1;
vuint32_t OU3:1;
vuint32_t OU2:1;
vuint32_t OU1:1;
vuint32_t OU0:1;
} B;
} OUDR; /* Output Update Disable Register */
uint32_t emios_reserved[5];
struct {
union {
vuint32_t R; /* Channel A Data Register */
} CADR;
union {
vuint32_t R; /* Channel B Data Register */
} CBDR;
union {
vuint32_t R; /* Channel Counter Register */
} CCNTR;
union {
vuint32_t R;
struct {
vuint32_t FREN:1;
vuint32_t ODIS:1;
vuint32_t ODISSL:2;
vuint32_t UCPRE:2;
vuint32_t UCPREN:1;
vuint32_t DMA:1;
vuint32_t:1;
vuint32_t IF:4;
vuint32_t FCK:1;
vuint32_t FEN:1;
vuint32_t:3;
vuint32_t FORCMA:1;
vuint32_t FORCMB:1;
vuint32_t:1;
vuint32_t BSL:2;
vuint32_t EDSEL:1;
vuint32_t EDPOL:1;
vuint32_t MODE:7;
} B;
} CCR; /* Channel Control Register */
union {
vuint32_t R;
struct {
vuint32_t OVR:1;
vuint32_t:15;
vuint32_t OVFL:1;
vuint32_t:12;
vuint32_t UCIN:1;
vuint32_t UCOUT:1;
vuint32_t FLAG:1;
} B;
} CSR; /* Channel Status Register */
uint32_t emios_channel_reserved[3];
} CH[24];
};
/****************************************************************************/
/* MODULE :ETPU */
/****************************************************************************/
/***************************Configuration Registers**************************/
struct ETPU_tag {
union { /* MODULE CONFIGURATION REGISTER */
vuint32_t R;
struct {
vuint32_t GEC:1; /* Global Exception Clear */
vuint32_t:3;
vuint32_t MGE1:1; /* Microcode Global Exception-ETPU_A */
vuint32_t MGE2:1; /* Microcode Global Exception-ETPU_B */
vuint32_t ILF1:1; /* Illegal Instruction Flag-ETPU_A */
vuint32_t ILF2:1; /* Illegal Instruction Flag-ETPU_B */
vuint32_t:3;
vuint32_t SCMSIZE:5; /* Shared Code Memory size */
vuint32_t:5;
vuint32_t SCMMISF:1; /* SCM MISC Flag */
vuint32_t SCMMISEN:1; /* SCM MISC Enable */
vuint32_t:2;
vuint32_t VIS:1; /* SCM Visability */
vuint32_t:5;
vuint32_t GTBE:1; /* Global Time Base Enable */
} B;
} MCR;
union { /* COHERENT DUAL-PARAMETER CONTROL */
vuint32_t R;
struct {
vuint32_t STS:1; /* Start Status bit */
vuint32_t CTBASE:5; /* Channel Transfer Base */
vuint32_t PBASE:10; /* Parameter Buffer Base Address */
vuint32_t PWIDTH:1; /* Parameter Width */
vuint32_t PARAM0:7; /* Channel Parameter 0 */
vuint32_t WR:1;
vuint32_t PARAM1:7; /* Channel Parameter 1 */
} B;
} CDCR;
uint32_t etpu_reserved1;
union { /* MISC Compare Register */
uint32_t R;
} MISCCMPR;
union { /* SCM off-range Date Register */
uint32_t R;
} SCMOFFDATAR;
union { /* ETPU_A Configuration Register */
vuint32_t R;
struct {
vuint32_t FEND:1; /* Force END */
vuint32_t MDIS:1; /* Low power Stop */
vuint32_t:1;
vuint32_t STF:1; /* Stop Flag */
vuint32_t:4;
vuint32_t HLTF:1; /* Halt Mode Flag */
vuint32_t:4;
vuint32_t FPSCK:3; /* Filter Prescaler Clock Control */
vuint32_t CDFC:2;
vuint32_t:9;
vuint32_t ETB:5; /* Entry Table Base */
} B;
} ECR_A;
union { /* ETPU_B Configuration Register */
vuint32_t R;
struct {
vuint32_t FEND:1; /* Force END */
vuint32_t MDIS:1; /* Low power Stop */
vuint32_t:1;
vuint32_t STF:1; /* Stop Flag */
vuint32_t:4;
vuint32_t HLTF:1; /* Halt Mode Flag */
vuint32_t:4;
vuint32_t FPSCK:3; /* Filter Prescaler Clock Control */
vuint32_t CDFC:2;
vuint32_t:9;
vuint32_t ETB:5; /* Entry Table Base */
} B;
} ECR_B;
uint32_t etpu_reserved4;
union { /* ETPU_A Timebase Configuration Register */
uint32_t R;
struct {
uint32_t TCR2CTL:3; /* TCR2 Clock/Gate Control */
uint32_t TCRCF:2; /* TCRCLK Signal Filter Control */
uint32_t:1;
uint32_t AM:1; /* Angle Mode */
uint32_t:3;
uint32_t TCR2P:6; /* TCR2 Prescaler Control */
uint32_t TCR1CTL:2; /* TCR1 Clock/Gate Control */
uint32_t:6;
uint32_t TCR1P:8; /* TCR1 Prescaler Control */
} B;
} TBCR_A;
union { /* ETPU_A TCR1 Visibility Register */
vuint32_t R;
} TB1R_A;
union { /* ETPU_A TCR2 Visibility Register */
vuint32_t R;
} TB2R_A;
union { /* ETPU_A STAC Configuration Register */
vuint32_t R;
struct {
vuint32_t REN1:1; /* Resource Enable TCR1 */
vuint32_t RSC1:1; /* Resource Control TCR1 */
vuint32_t:2;
vuint32_t SERVER_ID1:4;
vuint32_t:4;
vuint32_t SRV1:4; /* Resource Server Slot */
vuint32_t REN2:1; /* Resource Enable TCR2 */
vuint32_t RSC2:1; /* Resource Control TCR2 */
vuint32_t:2;
vuint32_t SERVER_ID2:4;
vuint32_t:4;
vuint32_t SRV2:4; /* Resource Server Slot */
} B;
} REDCR_A;
uint32_t etpu_reserved5[4];
union { /* ETPU_B Timebase Configuration Register */
uint32_t R;
struct {
uint32_t TCR2CTL:3; /* TCR2 Clock/Gate Control */
uint32_t TCRCF:2; /* TCRCLK Signal Filter Control */
uint32_t:1;
uint32_t AM:1; /* Angle Mode */
uint32_t:3;
uint32_t TCR2P:6; /* TCR2 Prescaler Control */
uint32_t TCR1CTL:2; /* TCR1 Clock/Gate Control */
uint32_t:6;
uint32_t TCR1P:8; /* TCR1 Prescaler Control */
} B;
} TBCR_B;
union { /* ETPU_B TCR1 Visibility Register */
vuint32_t R;
} TB1R_B;
union { /* ETPU_B TCR2 Visibility Register */
vuint32_t R;
} TB2R_B;
union { /* ETPU_B STAC Configuration Register */
vuint32_t R;
struct {
vuint32_t REN1:1; /* Resource Enable TCR1 */
vuint32_t RSC1:1; /* Resource Control TCR1 */
vuint32_t:2;
vuint32_t SERVER_ID1:4;
vuint32_t:4;
vuint32_t SRV1:4; /* Resource Server Slot */
vuint32_t REN2:1; /* Resource Enable TCR2 */
vuint32_t RSC2:1; /* Resource Control TCR2 */
vuint32_t:2;
vuint32_t SERVER_ID2:4;
vuint32_t:4;
vuint32_t SRV2:4; /* Resource Server Slot */
} B;
} REDCR_B;
uint32_t etpu_reserved7[108];
/*****************************Status and Control Registers**************************/
union { /* ETPU_A Channel Interrut Status */
vuint32_t R;
struct {
vuint32_t CIS31:1; /* Channel 31 Interrut Status */
vuint32_t CIS30:1; /* Channel 30 Interrut Status */
vuint32_t CIS29:1; /* Channel 29 Interrut Status */
vuint32_t CIS28:1; /* Channel 28 Interrut Status */
vuint32_t CIS27:1; /* Channel 27 Interrut Status */
vuint32_t CIS26:1; /* Channel 26 Interrut Status */
vuint32_t CIS25:1; /* Channel 25 Interrut Status */
vuint32_t CIS24:1; /* Channel 24 Interrut Status */
vuint32_t CIS23:1; /* Channel 23 Interrut Status */
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