📄 mpc5554.h
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/**************************************************************************/
/* FILE NAME: mpc5554.h COPYRIGHT (c) Freescale 2005 */
/* VERSION: 1.4 All Rights Reserved */
/* */
/* DESCRIPTION: */
/* This file contain all of the register and bit field definitions for */
/* MPC5554. */
/*========================================================================*/
/* UPDATE HISTORY */
/* REV AUTHOR DATE DESCRIPTION OF CHANGE */
/* --- ----------- --------- --------------------- */
/* 0.01 J. Loeliger 03/Mar/03 Initial version of file for MPC5554. */
/* Based on SoC version 0.7. */
/* 0.02 J. Loeliger 05/Mar/03 All registers and bit fields now */
/* defined. */
/* 0.03 J. Loeliger 05/May/03 Updated to current spec., fixed several*/
/* bugs and naming/formating issues. */
/* 0.04 J. Loeliger 16/May/03 More fixes and naming/formating issues.*/
/* 0.05 J. Loeliger 19/Aug/03 Updated for latest documentation. */
/* 0.06 J. Loeliger 03/Sep/03 Changed to include motint.h */
/* Updated many register names. */
/* 0.07 J. Loeliger 04/Nov/03 Changed to include typedefs.h and more */
/* register name updates. */
/* 0.08 J. Loeliger 25/Feb/04 Added MetroWerks #pragmas. */
/* Updated for user manual 1.0 */
/* 0.09 J. Loeliger 27/Feb/04 Updated eDMA tcd section and some more */
/* bit field names to match user's man. */
/* 0.10 J. Loeliger 01/Apr/04 Fixed register spacing in ADC and eTPU */
/* 0.11 J. Loeliger 16/Jun/04 Many fixes and updated to user's */
/* manual, also some testing done. */
/* 0.12 J. Loeliger 25/Jun/04 Fixed problems in edma and eTPU. */
/* 0.13 J. Loeliger 16/Jul/04 Fixed mistake in FlexCAN TIMER size and*/
/* changed eTPU memory defs to start with*/
/* ETPU_ */
/* 0.14 J. Loeliger 17/Nov/04 Added ETPU_CODE_RAM definition. */
/* All code moved to CVS repository. */
/* Updated copyright to Freescale. */
/* Added new SCMOFFDATAR register to eTPU*/
/* Fixed REDCR_A&B bit fields in eTPU. */
/* Added new DBR bit in CTAR for DSPI. */
/* 0.15 J. Loeliger 29/Nov/04 Added support for new eTPU util funcs. */
/* Added bit fields for FlexCAN buffer ID*/
/* 0.16 J. Loeliger 01/Dec/04 Corrected comments in release 0.16. */
/* 0.17 J. Loeliger 02/Dec/04 Moved eTPU variable definitions to a */
/* seperate new file. */
/* Removed SIU variable the GPIO */
/* routines do not need it. */
/* 1.0 G.Emerson 22/Feb/05 No real changes to this file. */
/* Joint generation with mpc5553.h */
/* 1.1 G. Emerson 6/Jun/05 Changes to SIU to allow for upward */
/* expansion of PCR/GPDI/GPDO */
/* Added #defines for memory sizes etc */
/* 1.2 G. Emerson 21/Sep/05 PBRIDGES fixes */
/* 1.3 G. Emerson 03/Jan/06 Pbridge MPCR/PACR/OPACR now generic */
/* XBAR MPR now generic */
/* ECSM has FSBMCR on all integrations */
/* 1.4 G. Emerson 24/Jan/06 Make Pbridges, XBAR, Flash BIU */
/* integration specific */
/**************************************************************************/
/*>>>>NOTE! this file is auto-generated please do not edit it!<<<<*/
#ifndef _MPC5554_H_
#define _MPC5554_H_
#include "typedefs.h"
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __MWERKS__
#pragma push
#pragma ANSI_strict off
#endif
/****************************************************************************/
/* MODULE : PBRIDGE_A Peripheral Bridge */
/****************************************************************************/
struct PBRIDGE_A_tag {
union {
vuint32_t R;
struct {
vuint32_t MBW0:1;
vuint32_t MTR0:1;
vuint32_t MTW0:1;
vuint32_t MPL0:1;
vuint32_t MBW1:1;
vuint32_t MTR1:1;
vuint32_t MTW1:1;
vuint32_t MPL1:1;
vuint32_t MBW2:1;
vuint32_t MTR2:1;
vuint32_t MTW2:1;
vuint32_t MPL2:1;
vuint32_t MBW3:1;
vuint32_t MTR3:1;
vuint32_t MTW3:1;
vuint32_t MPL3:1;
vuint32_t:4;
vuint32_t:4;
vuint32_t:4;
vuint32_t:4;
} B;
} MPCR; /* Master Privilege Control Register */
uint32_t pbridge_a_reserved2[7];
union {
vuint32_t R;
struct {
vuint32_t BW0:1;
vuint32_t SP0:1;
vuint32_t WP0:1;
vuint32_t TP0:1;
vuint32_t:28;
} B;
} PACR0;
uint32_t pbridge_a_reserved3[7];
union {
vuint32_t R;
struct {
vuint32_t BW0:1;
vuint32_t SP0:1;
vuint32_t WP0:1;
vuint32_t TP0:1;
vuint32_t BW1:1;
vuint32_t SP1:1;
vuint32_t WP1:1;
vuint32_t TP1:1;
vuint32_t BW2:1;
vuint32_t SP2:1;
vuint32_t WP2:1;
vuint32_t TP2:1;
vuint32_t:4;
vuint32_t BW4:1;
vuint32_t SP4:1;
vuint32_t WP4:1;
vuint32_t TP4:1;
vuint32_t:12;
} B;
} OPACR0;
union {
vuint32_t R;
struct {
vuint32_t BW0:1; /* EMIOS */
vuint32_t SP0:1;
vuint32_t WP0:1;
vuint32_t TP0:1;
vuint32_t:28;
} B;
} OPACR1;
union {
vuint32_t R;
struct {
vuint32_t BW0:1;
vuint32_t SP0:1;
vuint32_t WP0:1;
vuint32_t TP0:1;
vuint32_t:4;
vuint32_t BW2:1;
vuint32_t SP2:1;
vuint32_t WP2:1;
vuint32_t TP2:1;
vuint32_t BW3:1;
vuint32_t SP3:1;
vuint32_t WP3:1;
vuint32_t TP3:1;
vuint32_t BW4:1;
vuint32_t SP4:1;
vuint32_t WP4:1;
vuint32_t TP4:1;
vuint32_t:12;
} B;
} OPACR2;
};
/****************************************************************************/
/* MODULE : PBRIDGE_B Peripheral Bridge */
/****************************************************************************/
struct PBRIDGE_B_tag {
union {
vuint32_t R;
struct {
vuint32_t MBW0:1;
vuint32_t MTR0:1;
vuint32_t MTW0:1;
vuint32_t MPL0:1;
vuint32_t MBW1:1;
vuint32_t MTR1:1;
vuint32_t MTW1:1;
vuint32_t MPL1:1;
vuint32_t MBW2:1;
vuint32_t MTR2:1;
vuint32_t MTW2:1;
vuint32_t MPL2:1;
vuint32_t MBW3:1;
vuint32_t MTR3:1;
vuint32_t MTW3:1;
vuint32_t MPL3:1;
vuint32_t:4;
vuint32_t:4;
vuint32_t:4;
vuint32_t:4;
} B;
} MPCR; /* Master Privilege Control Register */
uint32_t pbridge_b_reserved2[7];
union {
vuint32_t R;
struct {
vuint32_t BW0:1;
vuint32_t SP0:1;
vuint32_t WP0:1;
vuint32_t TP0:1;
vuint32_t BW1:1;
vuint32_t SP1:1;
vuint32_t WP1:1;
vuint32_t TP1:1;
vuint32_t:24;
} B;
} PACR0;
uint32_t pbridge_b_reserved3;
union {
vuint32_t R;
struct {
vuint32_t BW0:1;
vuint32_t SP0:1;
vuint32_t WP0:1;
vuint32_t TP0:1;
vuint32_t BW1:1;
vuint32_t SP1:1;
vuint32_t WP1:1;
vuint32_t TP1:1;
vuint32_t BW2:1;
vuint32_t SP2:1;
vuint32_t WP2:1;
vuint32_t TP2:1;
vuint32_t:4;
vuint32_t:16;
} B;
} PACR2;
uint32_t pbridge_b_reserved4[5];
union {
vuint32_t R;
struct {
vuint32_t BW0:1;
vuint32_t SP0:1;
vuint32_t WP0:1;
vuint32_t TP0:1;
vuint32_t:12;
vuint32_t BW4:1; /* DSPI_A */
vuint32_t SP4:1;
vuint32_t WP4:1;
vuint32_t TP4:1;
vuint32_t BW5:1; /* DSPI_B */
vuint32_t SP5:1;
vuint32_t WP5:1;
vuint32_t TP5:1;
vuint32_t BW6:1;
vuint32_t SP6:1;
vuint32_t WP6:1;
vuint32_t TP6:1;
vuint32_t BW7:1;
vuint32_t SP7:1;
vuint32_t WP7:1;
vuint32_t TP7:1;
} B;
} OPACR0;
union {
vuint32_t R;
struct {
vuint32_t:16;
vuint32_t BW4:1;
vuint32_t SP4:1;
vuint32_t WP4:1;
vuint32_t TP4:1;
vuint32_t BW5:1; /* ESCI_B */
vuint32_t SP5:1;
vuint32_t WP5:1;
vuint32_t TP5:1;
vuint32_t:8;
} B;
} OPACR1;
union {
vuint32_t R;
struct {
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