📄 flash.dis
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{ SBP_Buf[brd_no].returnStat += SBP_RTSTUS_SXC_Veto;
d34: 3d 20 40 00 lis r9,16384
d38: 39 29 00 6c addi r9,r9,108
d3c: 88 1f 00 08 lbz r0,8(r31)
d40: 54 00 06 3e clrlwi r0,r0,24
d44: 1c 00 02 24 mulli r0,r0,548
d48: 7d 20 4a 14 add r9,r0,r9
d4c: 39 69 02 10 addi r11,r9,528
d50: 3d 20 40 00 lis r9,16384
d54: 39 29 00 6c addi r9,r9,108
d58: 88 1f 00 08 lbz r0,8(r31)
d5c: 54 00 06 3e clrlwi r0,r0,24
d60: 1c 00 02 24 mulli r0,r0,548
d64: 7d 20 4a 14 add r9,r0,r9
d68: 39 29 02 10 addi r9,r9,528
d6c: 89 29 00 08 lbz r9,8(r9)
d70: 38 09 00 64 addi r0,r9,100
d74: 98 0b 00 08 stb r0,8(r11)
..\src\FESC_src\/FESC_5554_SXC.c:24
//--------- for slave debugging ------
if(SBP_debug_info[brd_no] & REPORT_SLAVE_FAIL)
d78: 3d 20 40 00 lis r9,16384
d7c: 39 29 11 94 addi r9,r9,4500
d80: 88 1f 00 08 lbz r0,8(r31)
d84: 54 00 06 3e clrlwi r0,r0,24
d88: 7d 20 4a 14 add r9,r0,r9
d8c: 88 09 00 00 lbz r0,0(r9)
d90: 54 00 06 3e clrlwi r0,r0,24
d94: 54 00 07 38 rlwinm r0,r0,0,28,28
d98: 2f 80 00 00 cmpwi cr7,r0,0
d9c: 41 9e 00 28 beq- cr7,dc4 <SXC_master_verify+0x20c>
..\src\FESC_src\/FESC_5554_SXC.c:25
{ printp(send_c_ESCIA_dpb,"IOC板同步有问题！\n\r");
da0: 3d 20 00 00 lis r9,0
da4: 38 69 24 3c addi r3,r9,9276
da8: 3d 20 00 00 lis r9,0
dac: 38 89 7b ec addi r4,r9,31724
db0: 48 00 0c 6d bl 1a1c <printp>
..\src\FESC_src\/FESC_5554_SXC.c:26
dump_SXC_CH_info(brd_no);
db4: 88 1f 00 08 lbz r0,8(r31)
db8: 54 00 06 3e clrlwi r0,r0,24
dbc: 7c 03 03 78 mr r3,r0
dc0: 48 00 00 1d bl ddc <dump_SXC_CH_info>
..\src\FESC_src\/FESC_5554_SXC.c:29
}
}
}
dc4: 81 61 00 00 lwz r11,0(r1)
dc8: 80 0b 00 04 lwz r0,4(r11)
dcc: 7c 08 03 a6 mtlr r0
dd0: 83 eb ff fc lwz r31,-4(r11)
dd4: 7d 61 5b 78 mr r1,r11
dd8: 4e 80 00 20 blr
00000ddc <dump_SXC_CH_info>:
dump_SXC_CH_info():
..\src\FESC_src\/FESC_5554_SXC.c:36
/******************************************/
/* @2 */
/* ---------------------- */
/* */
/******************************************/
void dump_SXC_CH_info(uint8_t brd_no)
{
ddc: 94 21 ff c0 stwu r1,-64(r1)
de0: 7c 08 02 a6 mflr r0
de4: 93 61 00 2c stw r27,44(r1)
de8: 93 81 00 30 stw r28,48(r1)
dec: 93 a1 00 34 stw r29,52(r1)
df0: 93 e1 00 3c stw r31,60(r1)
df4: 90 01 00 44 stw r0,68(r1)
df8: 7c 3f 0b 78 mr r31,r1
dfc: 7c 60 1b 78 mr r0,r3
e00: 98 1f 00 20 stb r0,32(r31)
..\src\FESC_src\/FESC_5554_SXC.c:37
printp(send_c_ESCIA_dpb,"SXC info: B%d[%s] %d [SELF:%02X %02x %02X %02X] [MATE:%02X %02x %02X %02X]\n\r",
e04: 88 1f 00 20 lbz r0,32(r31)
e08: 54 0b 06 3e clrlwi r11,r0,24
e0c: 3d 20 40 00 lis r9,16384
e10: 39 29 00 00 addi r9,r9,0
e14: 88 1f 00 20 lbz r0,32(r31)
e18: 54 00 06 3e clrlwi r0,r0,24
e1c: 54 00 10 3a rlwinm r0,r0,2,0,29
e20: 7d 40 4a 14 add r10,r0,r9
e24: 3d 20 3f c0 lis r9,16320
e28: 88 1f 00 20 lbz r0,32(r31)
e2c: 54 00 06 3e clrlwi r0,r0,24
e30: 54 00 30 32 rlwinm r0,r0,6,0,25
e34: 7d 20 4a 14 add r9,r0,r9
e38: 39 29 00 04 addi r9,r9,4
e3c: 80 09 00 00 lwz r0,0(r9)
e40: 54 00 06 3e clrlwi r0,r0,24
e44: 54 08 07 be clrlwi r8,r0,30
e48: 3d 20 3f c0 lis r9,16320
e4c: 88 1f 00 20 lbz r0,32(r31)
e50: 54 00 06 3e clrlwi r0,r0,24
e54: 54 00 30 32 rlwinm r0,r0,6,0,25
e58: 7d 20 4a 14 add r9,r0,r9
e5c: 39 29 00 20 addi r9,r9,32
e60: 88 09 00 03 lbz r0,3(r9)
e64: 54 1d 06 3e clrlwi r29,r0,24
e68: 3d 20 3f c0 lis r9,16320
e6c: 88 1f 00 20 lbz r0,32(r31)
e70: 54 00 06 3e clrlwi r0,r0,24
e74: 54 00 30 32 rlwinm r0,r0,6,0,25
e78: 7d 20 4a 14 add r9,r0,r9
e7c: 39 29 00 20 addi r9,r9,32
e80: 88 09 00 07 lbz r0,7(r9)
e84: 54 1c 06 3e clrlwi r28,r0,24
e88: 3d 20 3f c0 lis r9,16320
e8c: 88 1f 00 20 lbz r0,32(r31)
e90: 54 00 06 3e clrlwi r0,r0,24
e94: 54 00 30 32 rlwinm r0,r0,6,0,25
e98: 7d 20 4a 14 add r9,r0,r9
e9c: 39 29 00 20 addi r9,r9,32
ea0: 88 09 00 0b lbz r0,11(r9)
ea4: 54 1b 06 3e clrlwi r27,r0,24
ea8: 3d 20 3f c0 lis r9,16320
eac: 88 1f 00 20 lbz r0,32(r31)
eb0: 54 00 06 3e clrlwi r0,r0,24
eb4: 54 00 30 32 rlwinm r0,r0,6,0,25
eb8: 7d 20 4a 14 add r9,r0,r9
ebc: 39 29 00 20 addi r9,r9,32
ec0: 88 09 00 0f lbz r0,15(r9)
ec4: 54 00 06 3e clrlwi r0,r0,24
ec8: 90 01 00 08 stw r0,8(r1)
ecc: 3d 20 3f c0 lis r9,16320
ed0: 88 1f 00 20 lbz r0,32(r31)
ed4: 54 00 06 3e clrlwi r0,r0,24
ed8: 54 00 30 32 rlwinm r0,r0,6,0,25
edc: 7d 20 4a 14 add r9,r0,r9
ee0: 39 29 00 30 addi r9,r9,48
ee4: 88 09 00 03 lbz r0,3(r9)
ee8: 54 00 06 3e clrlwi r0,r0,24
eec: 90 01 00 0c stw r0,12(r1)
ef0: 3d 20 3f c0 lis r9,16320
ef4: 88 1f 00 20 lbz r0,32(r31)
ef8: 54 00 06 3e clrlwi r0,r0,24
efc: 54 00 30 32 rlwinm r0,r0,6,0,25
f00: 7d 20 4a 14 add r9,r0,r9
f04: 39 29 00 30 addi r9,r9,48
f08: 88 09 00 07 lbz r0,7(r9)
f0c: 54 00 06 3e clrlwi r0,r0,24
f10: 90 01 00 10 stw r0,16(r1)
f14: 3d 20 3f c0 lis r9,16320
f18: 88 1f 00 20 lbz r0,32(r31)
f1c: 54 00 06 3e clrlwi r0,r0,24
f20: 54 00 30 32 rlwinm r0,r0,6,0,25
f24: 7d 20 4a 14 add r9,r0,r9
f28: 39 29 00 30 addi r9,r9,48
f2c: 88 09 00 0b lbz r0,11(r9)
f30: 54 00 06 3e clrlwi r0,r0,24
f34: 90 01 00 14 stw r0,20(r1)
f38: 3d 20 3f c0 lis r9,16320
f3c: 88 1f 00 20 lbz r0,32(r31)
f40: 54 00 06 3e clrlwi r0,r0,24
f44: 54 00 30 32 rlwinm r0,r0,6,0,25
f48: 7d 20 4a 14 add r9,r0,r9
f4c: 39 29 00 30 addi r9,r9,48
f50: 88 09 00 0f lbz r0,15(r9)
f54: 54 00 06 3e clrlwi r0,r0,24
f58: 90 01 00 18 stw r0,24(r1)
f5c: 3d 20 00 00 lis r9,0
f60: 38 69 24 3c addi r3,r9,9276
f64: 3d 20 00 00 lis r9,0
f68: 38 89 7c 00 addi r4,r9,31744
f6c: 7d 65 5b 78 mr r5,r11
f70: 80 ca 00 00 lwz r6,0(r10)
f74: 7d 07 43 78 mr r7,r8
f78: 7f a8 eb 78 mr r8,r29
f7c: 7f 89 e3 78 mr r9,r28
f80: 7f 6a db 78 mr r10,r27
f84: 4c c6 31 82 crclr 4*cr1+eq
f88: 48 00 0a 95 bl 1a1c <printp>
..\src\FESC_src\/FESC_5554_SXC.c:49
brd_no,
board_name[brd_no],
((uint8_t)SXC.CH[brd_no].SXC_SR.R & 0x03),
SXC.CH[brd_no].SELF_PCR.B.CNT,
SXC.CH[brd_no].SELF_WCR.B.CNT,
SXC.CH[brd_no].SELF_OUT_SPY_R.B.DATA,
SXC.CH[brd_no].SELF_IN_SPY_R.B.DATA,
SXC.CH[brd_no].MATE_PCR.B.CNT,
SXC.CH[brd_no].MATE_WCR.B.CNT,
SXC.CH[brd_no].MATE_OUT_SPY_R.B.DATA,
SXC.CH[brd_no].MATE_IN_SPY_R.B.DATA);
}
f8c: 81 61 00 00 lwz r11,0(r1)
f90: 80 0b 00 04 lwz r0,4(r11)
f94: 7c 08 03 a6 mtlr r0
f98: 83 6b ff ec lwz r27,-20(r11)
f9c: 83 8b ff f0 lwz r28,-16(r11)
fa0: 83 ab ff f4 lwz r29,-12(r11)
fa4: 83 eb ff fc lwz r31,-4(r11)
fa8: 7d 61 5b 78 mr r1,r11
fac: 4e 80 00 20 blr
00000fb0 <init_SXC>:
init_SXC():
..\src\FESC_src\/FESC_5554_SXC.c:57
/******************************************/
/* @2 */
/* ---------------------- */
/* */
/******************************************/
void init_SXC(void)
{ uint8_t i;
fb0: 94 21 ff e0 stwu r1,-32(r1)
fb4: 93 e1 00 1c stw r31,28(r1)
fb8: 7c 3f 0b 78 mr r31,r1
..\src\FESC_src\/FESC_5554_SXC.c:58
for(i=0;i<8;i++)
fbc: 38 00 00 00 li r0,0
fc0: 98 1f 00 08 stb r0,8(r31)
fc4: 88 1f 00 08 lbz r0,8(r31)
fc8: 54 00 06 3e clrlwi r0,r0,24
fcc: 2b 80 00 07 cmplwi cr7,r0,7
fd0: 41 9d 00 34 bgt- cr7,1004 <__STACK_SIZE+0x4>
..\src\FESC_src\/FESC_5554_SXC.c:60
{
SXC.CH[i].SXC_CR.B.PACKET_CNT_CLR = 1;
fd4: 3d 20 3f c0 lis r9,16320
fd8: 88 1f 00 08 lbz r0,8(r31)
fdc: 54 00 06 3e clrlwi r0,r0,24
fe0: 54 00 30 32 rlwinm r0,r0,6,0,25
fe4: 7d 20 4a 14 add r9,r0,r9
fe8: 88 09 00 03 lbz r0,3(r9)
fec: 60 00 00 02 ori r0,r0,2
ff0: 98 09 00 03 stb r0,3(r9)
..\src\FESC_src\/FESC_5554_SXC.c:58
ff4: 89 3f 00 08 lbz r9,8(r31)
ff8: 38 09 00 01 addi r0,r9,1
ffc: 98 1f 00 08 stb r0,8(r31)
1000: 4b ff ff c4 b fc4 <init_SXC+0x14>
..\src\FESC_src\/FESC_5554_SXC.c:63
//SXC.CH[i].SXC_CR.B.PACKET_START = 1;
}
}
1004: 81 61 00 00 lwz r11,0(r1)
1008: 83 eb ff fc lwz r31,-4(r11)
100c: 7d 61 5b 78 mr r1,r11
1010: 4e 80 00 20 blr
00001014 <init_EMIOS>:
init_EMIOS():
..\src\FESC_src\/FESC_5554_EMIOS.c:23
/* @2 */
/* ---------------------- */
/* */
/******************************************/
void init_EMIOS(void) {
1014: 94 21 ff e0 stwu r1,-32(r1)
1018: 7c 08 02 a6 mflr r0
101c: 93 e1 00 1c stw r31,28(r1)
1020: 90 01 00 24 stw r0,36(r1)
1024: 7c 3f 0b 78 mr r31,r1
..\src\FESC_src\/FESC_5554_EMIOS.c:25
uint8_t i;
EMIOS.MCR.B.GPRE= 119; /* Divide 120MHz sysclk by 119+1 for 1MHz eMIOS clk*/
1028: 3d 20 c3 fa lis r9,-15366
102c: 38 00 00 77 li r0,119
1030: 98 09 00 02 stb r0,2(r9)
..\src\FESC_src\/FESC_5554_EMIOS.c:27
//EMIOS.MCR.B.GPRE= 127; /* Divide 128MHz sysclk by 127+1 for 1MHz eMIOS clk*/
EMIOS.MCR.B.GPREN = 1; /* Enable eMIOS clock */
1034: 3d 20 c3 fa lis r9,-15366
1038: 88 09 00 00 lbz r0,0(r9)
103c: 60 00 00 04 ori r0,r0,4
1040: 98 09 00 00 stb r0,0(r9)
..\src\FESC_src\/FESC_5554_EMIOS.c:28
EMIOS.MCR.B.GTBE = 1; /* Enable global time base */
1044: 3d 20 c3 fa lis r9,-15366
1048: 88 09 00 00 lbz r0,0(r9)
104c: 60 00 00 10 ori r0,r0,16
1050: 98 09 00 00 stb r0,0(r9)
..\src\FESC_src\/FESC_5554_EMIOS.c:29
EMIOS.MCR.B.FRZ = 1; /* Enable stopping channels when in debug mode */
1054: 3d 20 c3 fa lis r9,-15366
1058: 88 09 00 00 lbz r0,0(r9)
105c: 60 00 00 20 ori r0,r0,32
1060: 98 09 00 00 stb r0,0(r9)
..\src\FESC_src\/FESC_5554_EMIOS.c:31
set_GPIO(PIN_EMIOS2,1);
1064: 38 60 00 b5 li r3,181
1068: 38 80 00 01 li r4,1
106c: 4b ff ef ed bl 58 <set_GPIO>
..\src\FESC_src\/FESC_5554_EMIOS.c:32
set_GPIO(PIN_EMIOS3,1);
1070: 38 60 00 b6 li r3,182
1074: 38 80 00 01 li r4,1
1078: 4b ff ef e1 bl 58 <set_GPIO>
..\src\FESC_src\/FESC_5554_EMIOS.c:33
set_GPIO(PIN_EMIOS4,1);
107c: 38 60 00 b7 li r3,183
1080: 38 80 00 01 li r4,1
1084: 4b ff ef d5 bl 58 <set_GPIO>
..\src\FESC_src\/FESC_5554_EMIOS.c:34
pad_func_config(PIN_EMIOS2,GPIO_FUNCTION | OUTPUT_MODE | DRIVE_STRENGTH_50PF ); //GPIO OUTPUT
1088: 38 60 00 b5 li r3,181
108c: 38 80 02 c0 li r4,704
1090: 4b ff ef 79 bl 8 <PEFILL>
..\src\FESC_src\/FESC_5554_EMIOS.c:35
pad_func_config(PIN_EMIOS3,GPIO_FUNCTION | OUTPUT_MODE | DRIVE_STRENGTH_50PF ); //GPIO OUTPUT
1094: 38 60 00 b6 li r3,182
1098: 38 80 02 c0 li r4,704
109c: 4b ff ef 6d bl 8 <PEFILL>
..\src\FESC_src\/FESC_5554_EMIOS.c:36
pad_func_config(PIN_EMIOS4,GPIO_FUNCTION | OUTPUT_MODE | DRIVE_STRENGTH_50PF ); //GPIO OUTPUT
10a0: 38 60 00 b7 li r3,183
10a4: 38 80 02 c0 li r4,704
10a8: 4b ff ef 61 bl 8 <PEFILL>
..\src\FESC_src\/FESC_5554_EMIOS.c:39
/* Setup EMIOS15-23 as LED control pins */
for(i=0;i<9;i++)
10ac: 38 00 00 00 li r0,0
10b0: 98 1f 00 08 stb r0,8(r31)
10b4: 88 1f 00 08 lbz r0,8(r31)
10b8: 54 00 06 3e clrlwi r0,r0,24
10bc: 2b 80 00 08 cmplwi cr7,r0,8
10c0: 41 9d 00 4c bgt- cr7,110c <init_EMIOS+0xf8>
..\src\FESC_src\/FESC_5554_EMIOS.c:40
{ pad_func_config(PIN_EMIOS15+i,GPIO_FUNCTION | OUTPUT_MODE | DRIVE_STRENGTH_50PF ); //GPIO OUTPUT
10c4: 88 1f 00 08 lbz r0,8(r31)
10c8: 54 09 06 3e clrlwi r9,r0,24
10cc: 38 09 00 c2 addi r0,r9,194
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