📄 flash.dis
字号:
960: 40 9e 00 10 bne- cr7,970 <FPGA_SPI_ready_read+0x44>
964: 38 00 00 01 li r0,1
968: 90 1f 00 0c stw r0,12(r31)
96c: 48 00 00 0c b 978 <FPGA_SPI_ready_read+0x4c>
..\src\FESC_src\/FESC_5554_FSPI.c:28
else return(0);
970: 38 00 00 00 li r0,0
974: 90 1f 00 0c stw r0,12(r31)
..\src\FESC_src\/FESC_5554_FSPI.c:29
}
978: 80 7f 00 0c lwz r3,12(r31)
97c: 81 61 00 00 lwz r11,0(r1)
980: 83 eb ff fc lwz r31,-4(r11)
984: 7d 61 5b 78 mr r1,r11
988: 4e 80 00 20 blr
0000098c <FPGA_SPI_Send>:
FPGA_SPI_Send():
..\src\FESC_src\/FESC_5554_FSPI.c:32
void FPGA_SPI_Send(uint8_t ch,uint8_t TxDATA)
{ SXC.CH[ch].SXC_CR.B.TCFC = 1;
98c: 94 21 ff e0 stwu r1,-32(r1)
990: 93 e1 00 1c stw r31,28(r1)
994: 7c 3f 0b 78 mr r31,r1
998: 7c 60 1b 78 mr r0,r3
99c: 7c 89 23 78 mr r9,r4
9a0: 98 1f 00 08 stb r0,8(r31)
9a4: 7d 20 4b 78 mr r0,r9
9a8: 98 1f 00 09 stb r0,9(r31)
9ac: 3d 20 3f c0 lis r9,16320
9b0: 88 1f 00 08 lbz r0,8(r31)
9b4: 54 00 06 3e clrlwi r0,r0,24
9b8: 54 00 30 32 rlwinm r0,r0,6,0,25
9bc: 7d 20 4a 14 add r9,r0,r9
9c0: 88 09 00 03 lbz r0,3(r9)
9c4: 64 00 ff ff oris r0,r0,65535
9c8: 60 00 ff 80 ori r0,r0,65408
9cc: 98 09 00 03 stb r0,3(r9)
..\src\FESC_src\/FESC_5554_FSPI.c:33
SXC.CH[ch].SPI_HOST_DATA_REG.B.DATA = TxDATA;
9d0: 3d 20 3f c0 lis r9,16320
9d4: 88 1f 00 08 lbz r0,8(r31)
9d8: 54 00 06 3e clrlwi r0,r0,24
9dc: 54 00 30 32 rlwinm r0,r0,6,0,25
9e0: 7d 20 4a 14 add r9,r0,r9
9e4: 88 1f 00 09 lbz r0,9(r31)
9e8: 98 09 00 0b stb r0,11(r9)
..\src\FESC_src\/FESC_5554_FSPI.c:34
SXC.CH[ch].SXC_CR.B.SEND = 1;
9ec: 3d 20 3f c0 lis r9,16320
9f0: 88 1f 00 08 lbz r0,8(r31)
9f4: 54 00 06 3e clrlwi r0,r0,24
9f8: 54 00 30 32 rlwinm r0,r0,6,0,25
9fc: 7d 20 4a 14 add r9,r0,r9
a00: 88 09 00 03 lbz r0,3(r9)
a04: 60 00 00 20 ori r0,r0,32
a08: 98 09 00 03 stb r0,3(r9)
..\src\FESC_src\/FESC_5554_FSPI.c:35
}
a0c: 81 61 00 00 lwz r11,0(r1)
a10: 83 eb ff fc lwz r31,-4(r11)
a14: 7d 61 5b 78 mr r1,r11
a18: 4e 80 00 20 blr
00000a1c <FPGA_SPI_Read>:
FPGA_SPI_Read():
..\src\FESC_src\/FESC_5554_FSPI.c:37
uint8_t FPGA_SPI_Read(uint8_t ch)
{
a1c: 94 21 ff e0 stwu r1,-32(r1)
a20: 93 e1 00 1c stw r31,28(r1)
a24: 7c 3f 0b 78 mr r31,r1
a28: 7c 60 1b 78 mr r0,r3
a2c: 98 1f 00 08 stb r0,8(r31)
..\src\FESC_src\/FESC_5554_FSPI.c:38
SXC.CH[ch].SXC_CR.B.RDFC = 1;
a30: 3d 20 3f c0 lis r9,16320
a34: 88 1f 00 08 lbz r0,8(r31)
a38: 54 00 06 3e clrlwi r0,r0,24
a3c: 54 00 30 32 rlwinm r0,r0,6,0,25
a40: 7d 20 4a 14 add r9,r0,r9
a44: 88 09 00 03 lbz r0,3(r9)
a48: 60 00 00 40 ori r0,r0,64
a4c: 98 09 00 03 stb r0,3(r9)
..\src\FESC_src\/FESC_5554_FSPI.c:39
return(SXC.CH[ch].SPI_HOST_DATA_REG.B.DATA);
a50: 3d 20 3f c0 lis r9,16320
a54: 88 1f 00 08 lbz r0,8(r31)
a58: 54 00 06 3e clrlwi r0,r0,24
a5c: 54 00 30 32 rlwinm r0,r0,6,0,25
a60: 7d 20 4a 14 add r9,r0,r9
a64: 88 09 00 0b lbz r0,11(r9)
a68: 54 00 06 3e clrlwi r0,r0,24
a6c: 54 00 06 3e clrlwi r0,r0,24
..\src\FESC_src\/FESC_5554_FSPI.c:40
}
a70: 7c 03 03 78 mr r3,r0
a74: 81 61 00 00 lwz r11,0(r1)
a78: 83 eb ff fc lwz r31,-4(r11)
a7c: 7d 61 5b 78 mr r1,r11
a80: 4e 80 00 20 blr
00000a84 <FPGA_SPI_Swap>:
FPGA_SPI_Swap():
..\src\FESC_src\/FESC_5554_FSPI.c:44
uint8_t FPGA_SPI_Swap(uint8_t ch,uint8_t TxDATA)
{
a84: 94 21 ff e0 stwu r1,-32(r1)
a88: 93 e1 00 1c stw r31,28(r1)
a8c: 7c 3f 0b 78 mr r31,r1
a90: 7c 60 1b 78 mr r0,r3
a94: 7c 89 23 78 mr r9,r4
a98: 98 1f 00 08 stb r0,8(r31)
a9c: 7d 20 4b 78 mr r0,r9
aa0: 98 1f 00 09 stb r0,9(r31)
..\src\FESC_src\/FESC_5554_FSPI.c:45
if((SXC.CH[ch].SXC_SR.B.BUSY == 0) && (SXC.CH[3].SXC_SR.B.TCF == 0))
aa4: 3d 20 3f c0 lis r9,16320
aa8: 88 1f 00 08 lbz r0,8(r31)
aac: 54 00 06 3e clrlwi r0,r0,24
ab0: 54 00 30 32 rlwinm r0,r0,6,0,25
ab4: 7d 20 4a 14 add r9,r0,r9
ab8: 88 09 00 07 lbz r0,7(r9)
abc: 54 00 df fe rlwinm r0,r0,27,31,31
ac0: 2f 80 00 00 cmpwi cr7,r0,0
ac4: 40 9e 00 34 bne- cr7,af8 <FPGA_SPI_Swap+0x74>
ac8: 3d 20 3f c0 lis r9,16320
acc: 88 09 00 c7 lbz r0,199(r9)
ad0: 54 00 cf fe rlwinm r0,r0,25,31,31
ad4: 2f 80 00 00 cmpwi cr7,r0,0
ad8: 40 9e 00 20 bne- cr7,af8 <FPGA_SPI_Swap+0x74>
..\src\FESC_src\/FESC_5554_FSPI.c:46
SXC.CH[ch].SPI_HOST_DATA_REG.B.DATA = TxDATA;
adc: 3d 20 3f c0 lis r9,16320
ae0: 88 1f 00 08 lbz r0,8(r31)
ae4: 54 00 06 3e clrlwi r0,r0,24
ae8: 54 00 30 32 rlwinm r0,r0,6,0,25
aec: 7d 20 4a 14 add r9,r0,r9
af0: 88 1f 00 09 lbz r0,9(r31)
af4: 98 09 00 0b stb r0,11(r9)
..\src\FESC_src\/FESC_5554_FSPI.c:47
SXC.CH[ch].SXC_CR.B.SEND = 1;
af8: 3d 20 3f c0 lis r9,16320
afc: 88 1f 00 08 lbz r0,8(r31)
b00: 54 00 06 3e clrlwi r0,r0,24
b04: 54 00 30 32 rlwinm r0,r0,6,0,25
b08: 7d 20 4a 14 add r9,r0,r9
b0c: 88 09 00 03 lbz r0,3(r9)
b10: 60 00 00 20 ori r0,r0,32
b14: 98 09 00 03 stb r0,3(r9)
..\src\FESC_src\/FESC_5554_FSPI.c:48
while(SXC.CH[ch].SXC_SR.B.BUSY == 1){}
b18: 3d 20 3f c0 lis r9,16320
b1c: 88 1f 00 08 lbz r0,8(r31)
b20: 54 00 06 3e clrlwi r0,r0,24
b24: 54 00 30 32 rlwinm r0,r0,6,0,25
b28: 7d 20 4a 14 add r9,r0,r9
b2c: 88 09 00 07 lbz r0,7(r9)
b30: 54 00 df fe rlwinm r0,r0,27,31,31
b34: 2f 80 00 01 cmpwi cr7,r0,1
b38: 40 9e 00 08 bne- cr7,b40 <FPGA_SPI_Swap+0xbc>
b3c: 4b ff ff dc b b18 <FPGA_SPI_Swap+0x94>
..\src\FESC_src\/FESC_5554_FSPI.c:49
SXC.CH[ch].SXC_CR.B.TCFC = 1;
b40: 3d 20 3f c0 lis r9,16320
b44: 88 1f 00 08 lbz r0,8(r31)
b48: 54 00 06 3e clrlwi r0,r0,24
b4c: 54 00 30 32 rlwinm r0,r0,6,0,25
b50: 7d 20 4a 14 add r9,r0,r9
b54: 88 09 00 03 lbz r0,3(r9)
b58: 64 00 ff ff oris r0,r0,65535
b5c: 60 00 ff 80 ori r0,r0,65408
b60: 98 09 00 03 stb r0,3(r9)
..\src\FESC_src\/FESC_5554_FSPI.c:50
SXC.CH[ch].SXC_CR.B.RDFC = 1;
b64: 3d 20 3f c0 lis r9,16320
b68: 88 1f 00 08 lbz r0,8(r31)
b6c: 54 00 06 3e clrlwi r0,r0,24
b70: 54 00 30 32 rlwinm r0,r0,6,0,25
b74: 7d 20 4a 14 add r9,r0,r9
b78: 88 09 00 03 lbz r0,3(r9)
b7c: 60 00 00 40 ori r0,r0,64
b80: 98 09 00 03 stb r0,3(r9)
..\src\FESC_src\/FESC_5554_FSPI.c:51
return(SXC.CH[ch].SPI_HOST_DATA_REG.B.DATA);
b84: 3d 20 3f c0 lis r9,16320
b88: 88 1f 00 08 lbz r0,8(r31)
b8c: 54 00 06 3e clrlwi r0,r0,24
b90: 54 00 30 32 rlwinm r0,r0,6,0,25
b94: 7d 20 4a 14 add r9,r0,r9
b98: 88 09 00 0b lbz r0,11(r9)
b9c: 54 00 06 3e clrlwi r0,r0,24
ba0: 54 00 06 3e clrlwi r0,r0,24
..\src\FESC_src\/FESC_5554_FSPI.c:52
}
ba4: 7c 03 03 78 mr r3,r0
ba8: 81 61 00 00 lwz r11,0(r1)
bac: 83 eb ff fc lwz r31,-4(r11)
bb0: 7d 61 5b 78 mr r1,r11
bb4: 4e 80 00 20 blr
00000bb8 <SXC_master_verify>:
SXC_master_verify():
..\src\FESC_src\/FESC_5554_SXC.c:7
/* ---------------------- */
/* */
/******************************************/
void SXC_master_verify(uint8_t brd_no)
{
bb8: 94 21 ff e0 stwu r1,-32(r1)
bbc: 7c 08 02 a6 mflr r0
bc0: 93 e1 00 1c stw r31,28(r1)
bc4: 90 01 00 24 stw r0,36(r1)
bc8: 7c 3f 0b 78 mr r31,r1
bcc: 7c 60 1b 78 mr r0,r3
bd0: 98 1f 00 08 stb r0,8(r31)
..\src\FESC_src\/FESC_5554_SXC.c:8
if( SXC.CH[brd_no].SXC_SR.B.master_fail_first
bd4: 3d 20 3f c0 lis r9,16320
bd8: 88 1f 00 08 lbz r0,8(r31)
bdc: 54 00 06 3e clrlwi r0,r0,24
be0: 54 00 30 32 rlwinm r0,r0,6,0,25
be4: 7d 20 4a 14 add r9,r0,r9
be8: 88 09 00 07 lbz r0,7(r9)
bec: 54 00 ff fe rlwinm r0,r0,31,31,31
bf0: 2f 80 00 00 cmpwi cr7,r0,0
bf4: 40 9e 00 50 bne- cr7,c44 <SXC_master_verify+0x8c>
bf8: 3d 20 3f c0 lis r9,16320
bfc: 88 1f 00 08 lbz r0,8(r31)
c00: 54 00 06 3e clrlwi r0,r0,24
c04: 54 00 30 32 rlwinm r0,r0,6,0,25
c08: 7d 20 4a 14 add r9,r0,r9
c0c: 39 69 00 20 addi r11,r9,32
c10: 3d 20 3f c0 lis r9,16320
c14: 88 1f 00 08 lbz r0,8(r31)
c18: 54 00 06 3e clrlwi r0,r0,24
c1c: 54 00 30 32 rlwinm r0,r0,6,0,25
c20: 7d 20 4a 14 add r9,r0,r9
c24: 39 29 00 30 addi r9,r9,48
c28: 88 0b 00 03 lbz r0,3(r11)
c2c: 54 0b 06 3e clrlwi r11,r0,24
c30: 88 09 00 03 lbz r0,3(r9)
c34: 54 00 06 3e clrlwi r0,r0,24
c38: 7f 8b 00 00 cmpw cr7,r11,r0
c3c: 40 9e 00 08 bne- cr7,c44 <SXC_master_verify+0x8c>
c40: 48 00 00 84 b cc4 <SXC_master_verify+0x10c>
..\src\FESC_src\/FESC_5554_SXC.c:11
||(SXC.CH[brd_no].SELF_PCR.B.CNT != SXC.CH[brd_no].MATE_PCR.B.CNT)
)
{ SBP_Buf[brd_no].returnStat += SBP_RTSTUS_SXC_Veto;
c44: 3d 20 40 00 lis r9,16384
c48: 39 29 00 6c addi r9,r9,108
c4c: 88 1f 00 08 lbz r0,8(r31)
c50: 54 00 06 3e clrlwi r0,r0,24
c54: 1c 00 02 24 mulli r0,r0,548
c58: 7d 20 4a 14 add r9,r0,r9
c5c: 39 69 02 10 addi r11,r9,528
c60: 3d 20 40 00 lis r9,16384
c64: 39 29 00 6c addi r9,r9,108
c68: 88 1f 00 08 lbz r0,8(r31)
c6c: 54 00 06 3e clrlwi r0,r0,24
c70: 1c 00 02 24 mulli r0,r0,548
c74: 7d 20 4a 14 add r9,r0,r9
c78: 39 29 02 10 addi r9,r9,528
c7c: 89 29 00 08 lbz r9,8(r9)
c80: 38 09 00 64 addi r0,r9,100
c84: 98 0b 00 08 stb r0,8(r11)
..\src\FESC_src\/FESC_5554_SXC.c:12
dump_SXC_CH_info(brd_no);
c88: 88 1f 00 08 lbz r0,8(r31)
c8c: 54 00 06 3e clrlwi r0,r0,24
c90: 7c 03 03 78 mr r3,r0
c94: 48 00 01 49 bl ddc <dump_SXC_CH_info>
..\src\FESC_src\/FESC_5554_SXC.c:13
dump_SBP_lastPack(brd_no);
c98: 88 1f 00 08 lbz r0,8(r31)
c9c: 54 00 06 3e clrlwi r0,r0,24
ca0: 7c 03 03 78 mr r3,r0
ca4: 48 00 44 bd bl 5160 <dump_SBP_lastPack>
..\src\FESC_src\/FESC_5554_SXC.c:14
printp(send_c_ESCIA_dpb,"n\r主控制板取2失败\n\r");
ca8: 3d 20 00 00 lis r9,0
cac: 38 69 24 3c addi r3,r9,9276
cb0: 3d 20 00 00 lis r9,0
cb4: 38 89 7b d8 addi r4,r9,31704
cb8: 48 00 0d 65 bl 1a1c <printp>
..\src\FESC_src\/FESC_5554_SXC.c:16
command_line_interface();
cbc: 48 00 4b ed bl 58a8 <command_line_interface>
..\src\FESC_src\/FESC_5554_SXC.c:17
while(1){}
cc0: 48 00 00 00 b cc0 <SXC_master_verify+0x108>
..\src\FESC_src\/FESC_5554_SXC.c:19
}
if( SXC.CH[brd_no].SXC_SR.B.slave_fail_first
cc4: 3d 20 3f c0 lis r9,16320
cc8: 88 1f 00 08 lbz r0,8(r31)
ccc: 54 00 06 3e clrlwi r0,r0,24
cd0: 54 00 30 32 rlwinm r0,r0,6,0,25
cd4: 7d 20 4a 14 add r9,r0,r9
cd8: 88 09 00 07 lbz r0,7(r9)
cdc: 54 00 07 fe clrlwi r0,r0,31
ce0: 2f 80 00 00 cmpwi cr7,r0,0
ce4: 40 9e 00 50 bne- cr7,d34 <SXC_master_verify+0x17c>
ce8: 3d 20 3f c0 lis r9,16320
cec: 88 1f 00 08 lbz r0,8(r31)
cf0: 54 00 06 3e clrlwi r0,r0,24
cf4: 54 00 30 32 rlwinm r0,r0,6,0,25
cf8: 7d 20 4a 14 add r9,r0,r9
cfc: 39 69 00 20 addi r11,r9,32
d00: 3d 20 3f c0 lis r9,16320
d04: 88 1f 00 08 lbz r0,8(r31)
d08: 54 00 06 3e clrlwi r0,r0,24
d0c: 54 00 30 32 rlwinm r0,r0,6,0,25
d10: 7d 20 4a 14 add r9,r0,r9
d14: 39 29 00 30 addi r9,r9,48
d18: 88 0b 00 07 lbz r0,7(r11)
d1c: 54 0b 06 3e clrlwi r11,r0,24
d20: 88 09 00 07 lbz r0,7(r9)
d24: 54 00 06 3e clrlwi r0,r0,24
d28: 7f 8b 00 00 cmpw cr7,r11,r0
d2c: 40 9e 00 08 bne- cr7,d34 <SXC_master_verify+0x17c>
d30: 48 00 00 94 b dc4 <SXC_master_verify+0x20c>
..\src\FESC_src\/FESC_5554_SXC.c:22
||(SXC.CH[brd_no].SELF_WCR.B.CNT != SXC.CH[brd_no].MATE_WCR.B.CNT)
)
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