📄 flash.dis
字号:
pad_func_config(PIN_RXD_A_GPIO90,PRIMARY_FUNCTION); //SCI
628: 38 60 00 5a li r3,90
62c: 38 80 0c 00 li r4,3072
630: 4b ff f9 d9 bl 8 <PEFILL>
..\src\FESC_src\/FESC_5554_ESCI.c:19
//ESCI_B.CR1.B.SBR = 781; //
//ESCI_B.CR1.B.TE = 1;
//ESCI_B.CR1.B.RE = 1;
ESCI_B.CR1.R = 0x0187000C;
634: 3d 20 ff fb lis r9,-5
638: 61 29 40 00 ori r9,r9,16384
63c: 3c 00 01 87 lis r0,391
640: 60 00 00 0c ori r0,r0,12
644: 90 09 00 00 stw r0,0(r9)
..\src\FESC_src\/FESC_5554_ESCI.c:20
pad_func_config(PIN_TXD_B_GPIO91,PRIMARY_FUNCTION); //SCI
648: 38 60 00 5b li r3,91
64c: 38 80 0c 00 li r4,3072
650: 4b ff f9 b9 bl 8 <PEFILL>
..\src\FESC_src\/FESC_5554_ESCI.c:21
pad_func_config(PIN_RXD_B_GPIO92,PRIMARY_FUNCTION); //SCI
654: 38 60 00 5c li r3,92
658: 38 80 0c 00 li r4,3072
65c: 4b ff f9 ad bl 8 <PEFILL>
..\src\FESC_src\/FESC_5554_ESCI.c:22
}
660: 81 61 00 00 lwz r11,0(r1)
664: 80 0b 00 04 lwz r0,4(r11)
668: 7c 08 03 a6 mtlr r0
66c: 83 eb ff fc lwz r31,-4(r11)
670: 7d 61 5b 78 mr r1,r11
674: 4e 80 00 20 blr
00000678 <send_c_ESCIA>:
send_c_ESCIA():
..\src\FESC_src\/FESC_5554_ESCI.c:25
void send_c_ESCIA(uint8_t schar)
{
678: 94 21 ff e0 stwu r1,-32(r1)
67c: 93 e1 00 1c stw r31,28(r1)
680: 7c 3f 0b 78 mr r31,r1
684: 7c 60 1b 78 mr r0,r3
688: 98 1f 00 08 stb r0,8(r31)
..\src\FESC_src\/FESC_5554_ESCI.c:26
while(ESCI_A.SR.B.TDRE ==0) {}
68c: 3d 20 ff fb lis r9,-5
690: 88 09 00 08 lbz r0,8(r9)
694: 54 00 cf fe rlwinm r0,r0,25,31,31
698: 2f 80 00 00 cmpwi cr7,r0,0
69c: 40 9e 00 08 bne- cr7,6a4 <send_c_ESCIA+0x2c>
6a0: 4b ff ff ec b 68c <send_c_ESCIA+0x14>
..\src\FESC_src\/FESC_5554_ESCI.c:27
ESCI_A.SR.R = 0x80000000;
6a4: 3d 20 ff fb lis r9,-5
6a8: 3c 00 80 00 lis r0,-32768
6ac: 90 09 00 08 stw r0,8(r9)
..\src\FESC_src\/FESC_5554_ESCI.c:28
ESCI_A.DR.B.D = schar;
6b0: 3d 20 ff fb lis r9,-5
6b4: 88 1f 00 08 lbz r0,8(r31)
6b8: 98 09 00 07 stb r0,7(r9)
..\src\FESC_src\/FESC_5554_ESCI.c:29
}
6bc: 81 61 00 00 lwz r11,0(r1)
6c0: 83 eb ff fc lwz r31,-4(r11)
6c4: 7d 61 5b 78 mr r1,r11
6c8: 4e 80 00 20 blr
000006cc <get_c_ESCI_A>:
get_c_ESCI_A():
..\src\FESC_src\/FESC_5554_ESCI.c:32
uint8_t get_c_ESCI_A(void)
{ uint8_t RecData;
6cc: 94 21 ff e0 stwu r1,-32(r1)
6d0: 93 e1 00 1c stw r31,28(r1)
6d4: 7c 3f 0b 78 mr r31,r1
..\src\FESC_src\/FESC_5554_ESCI.c:33
while(ESCI_A.SR.B.RDRF == 0 ) {}
6d8: 3d 20 ff fb lis r9,-5
6dc: 88 09 00 08 lbz r0,8(r9)
6e0: 54 00 df fe rlwinm r0,r0,27,31,31
6e4: 2f 80 00 00 cmpwi cr7,r0,0
6e8: 40 9e 00 08 bne- cr7,6f0 <get_c_ESCI_A+0x24>
6ec: 4b ff ff ec b 6d8 <get_c_ESCI_A+0xc>
..\src\FESC_src\/FESC_5554_ESCI.c:34
RecData = ESCI_A.DR.B.D;
6f0: 3d 20 ff fb lis r9,-5
6f4: 88 09 00 07 lbz r0,7(r9)
6f8: 98 1f 00 08 stb r0,8(r31)
..\src\FESC_src\/FESC_5554_ESCI.c:35
ESCI_A.SR.R = 0x20000000;
6fc: 3d 20 ff fb lis r9,-5
700: 3c 00 20 00 lis r0,8192
704: 90 09 00 08 stw r0,8(r9)
..\src\FESC_src\/FESC_5554_ESCI.c:36
return(RecData);
708: 88 1f 00 08 lbz r0,8(r31)
70c: 54 00 06 3e clrlwi r0,r0,24
..\src\FESC_src\/FESC_5554_ESCI.c:37
}
710: 7c 03 03 78 mr r3,r0
714: 81 61 00 00 lwz r11,0(r1)
718: 83 eb ff fc lwz r31,-4(r11)
71c: 7d 61 5b 78 mr r1,r11
720: 4e 80 00 20 blr
00000724 <send_c_ESCIB>:
send_c_ESCIB():
..\src\FESC_src\/FESC_5554_ESCI.c:40
void send_c_ESCIB(uint8_t schar)
{
724: 94 21 ff e0 stwu r1,-32(r1)
728: 93 e1 00 1c stw r31,28(r1)
72c: 7c 3f 0b 78 mr r31,r1
730: 7c 60 1b 78 mr r0,r3
734: 98 1f 00 08 stb r0,8(r31)
..\src\FESC_src\/FESC_5554_ESCI.c:41
while(ESCI_B.SR.B.TDRE == 1){}
738: 3d 20 ff fb lis r9,-5
73c: 61 29 40 00 ori r9,r9,16384
740: 88 09 00 08 lbz r0,8(r9)
744: 54 00 cf fe rlwinm r0,r0,25,31,31
748: 2f 80 00 01 cmpwi cr7,r0,1
74c: 40 9e 00 08 bne- cr7,754 <send_c_ESCIB+0x30>
750: 4b ff ff e8 b 738 <send_c_ESCIB+0x14>
..\src\FESC_src\/FESC_5554_ESCI.c:42
ESCI_B.SR.R = 0x80000000;
754: 3d 20 ff fb lis r9,-5
758: 61 29 40 00 ori r9,r9,16384
75c: 3c 00 80 00 lis r0,-32768
760: 90 09 00 08 stw r0,8(r9)
..\src\FESC_src\/FESC_5554_ESCI.c:43
ESCI_B.DR.B.D = schar;
764: 3d 20 ff fb lis r9,-5
768: 61 29 40 00 ori r9,r9,16384
76c: 88 1f 00 08 lbz r0,8(r31)
770: 98 09 00 07 stb r0,7(r9)
..\src\FESC_src\/FESC_5554_ESCI.c:44
}
774: 81 61 00 00 lwz r11,0(r1)
778: 83 eb ff fc lwz r31,-4(r11)
77c: 7d 61 5b 78 mr r1,r11
780: 4e 80 00 20 blr
00000784 <get_c_ESCI_B>:
get_c_ESCI_B():
..\src\FESC_src\/FESC_5554_ESCI.c:47
uint8_t get_c_ESCI_B(void)
{ uint8_t RecData;
784: 94 21 ff e0 stwu r1,-32(r1)
788: 93 e1 00 1c stw r31,28(r1)
78c: 7c 3f 0b 78 mr r31,r1
..\src\FESC_src\/FESC_5554_ESCI.c:48
while(ESCI_B.SR.B.RDRF == 0 ) {}
790: 3d 20 ff fb lis r9,-5
794: 61 29 40 00 ori r9,r9,16384
798: 88 09 00 08 lbz r0,8(r9)
79c: 54 00 df fe rlwinm r0,r0,27,31,31
7a0: 2f 80 00 00 cmpwi cr7,r0,0
7a4: 40 9e 00 08 bne- cr7,7ac <get_c_ESCI_B+0x28>
7a8: 4b ff ff e8 b 790 <get_c_ESCI_B+0xc>
..\src\FESC_src\/FESC_5554_ESCI.c:49
RecData = ESCI_B.DR.B.D;
7ac: 3d 20 ff fb lis r9,-5
7b0: 61 29 40 00 ori r9,r9,16384
7b4: 88 09 00 07 lbz r0,7(r9)
7b8: 98 1f 00 08 stb r0,8(r31)
..\src\FESC_src\/FESC_5554_ESCI.c:50
ESCI_B.SR.R = 0x20000000;
7bc: 3d 20 ff fb lis r9,-5
7c0: 61 29 40 00 ori r9,r9,16384
7c4: 3c 00 20 00 lis r0,8192
7c8: 90 09 00 08 stw r0,8(r9)
..\src\FESC_src\/FESC_5554_ESCI.c:51
return(RecData);
7cc: 88 1f 00 08 lbz r0,8(r31)
7d0: 54 00 06 3e clrlwi r0,r0,24
..\src\FESC_src\/FESC_5554_ESCI.c:52
}
7d4: 7c 03 03 78 mr r3,r0
7d8: 81 61 00 00 lwz r11,0(r1)
7dc: 83 eb ff fc lwz r31,-4(r11)
7e0: 7d 61 5b 78 mr r1,r11
7e4: 4e 80 00 20 blr
000007e8 <init_FPGA_SPI>:
init_FPGA_SPI():
..\src\FESC_src\/FESC_5554_FSPI.c:9
/* RETURN NOTES : None */
/* WARNING : None */
/*************************************************************************/
void init_FPGA_SPI(void)
{ uint8_t i;
7e8: 94 21 ff e0 stwu r1,-32(r1)
7ec: 93 e1 00 1c stw r31,28(r1)
7f0: 7c 3f 0b 78 mr r31,r1
..\src\FESC_src\/FESC_5554_FSPI.c:10
for(i=0;i<8;i++)
7f4: 38 00 00 00 li r0,0
7f8: 98 1f 00 08 stb r0,8(r31)
7fc: 88 1f 00 08 lbz r0,8(r31)
800: 54 00 06 3e clrlwi r0,r0,24
804: 2b 80 00 07 cmplwi cr7,r0,7
808: 41 9d 00 58 bgt- cr7,860 <DEPTH_2+0x60>
..\src\FESC_src\/FESC_5554_FSPI.c:12
{
SXC.CH[i].SXC_CR.B.TCFC = 1;
80c: 3d 20 3f c0 lis r9,16320
810: 88 1f 00 08 lbz r0,8(r31)
814: 54 00 06 3e clrlwi r0,r0,24
818: 54 00 30 32 rlwinm r0,r0,6,0,25
81c: 7d 20 4a 14 add r9,r0,r9
820: 88 09 00 03 lbz r0,3(r9)
824: 64 00 ff ff oris r0,r0,65535
828: 60 00 ff 80 ori r0,r0,65408
82c: 98 09 00 03 stb r0,3(r9)
..\src\FESC_src\/FESC_5554_FSPI.c:13
SXC.CH[i].SXC_CR.B.RDFC = 1;
830: 3d 20 3f c0 lis r9,16320
834: 88 1f 00 08 lbz r0,8(r31)
838: 54 00 06 3e clrlwi r0,r0,24
83c: 54 00 30 32 rlwinm r0,r0,6,0,25
840: 7d 20 4a 14 add r9,r0,r9
844: 88 09 00 03 lbz r0,3(r9)
848: 60 00 00 40 ori r0,r0,64
84c: 98 09 00 03 stb r0,3(r9)
..\src\FESC_src\/FESC_5554_FSPI.c:10
850: 89 3f 00 08 lbz r9,8(r31)
854: 38 09 00 01 addi r0,r9,1
858: 98 1f 00 08 stb r0,8(r31)
85c: 4b ff ff a0 b 7fc <init_FPGA_SPI+0x14>
..\src\FESC_src\/FESC_5554_FSPI.c:15
}
for(i=0;i<6;i++) SXC.CH[i].SPI_BAUD_REG.B.BAUD = 25; // 120MHz/(32*25) = 150Kbps
860: 38 00 00 00 li r0,0
864: 98 1f 00 08 stb r0,8(r31)
868: 88 1f 00 08 lbz r0,8(r31)
86c: 54 00 06 3e clrlwi r0,r0,24
870: 2b 80 00 05 cmplwi cr7,r0,5
874: 41 9d 00 30 bgt- cr7,8a4 <DEPTH_2+0xa4>
878: 3d 20 3f c0 lis r9,16320
87c: 88 1f 00 08 lbz r0,8(r31)
880: 54 00 06 3e clrlwi r0,r0,24
884: 54 00 30 32 rlwinm r0,r0,6,0,25
888: 7d 20 4a 14 add r9,r0,r9
88c: 38 00 00 19 li r0,25
890: 98 09 00 0f stb r0,15(r9)
894: 89 3f 00 08 lbz r9,8(r31)
898: 38 09 00 01 addi r0,r9,1
89c: 98 1f 00 08 stb r0,8(r31)
8a0: 4b ff ff c8 b 868 <DEPTH_2+0x68>
..\src\FESC_src\/FESC_5554_FSPI.c:16
SXC.CH[6].SPI_BAUD_REG.B.BAUD = 5; // 120MHz/(32*5) = 750Kbps
8a4: 3d 20 3f c0 lis r9,16320
8a8: 38 00 00 05 li r0,5
8ac: 98 09 01 8f stb r0,399(r9)
..\src\FESC_src\/FESC_5554_FSPI.c:17
SXC.CH[7].SPI_BAUD_REG.B.BAUD = 5;
8b0: 3d 20 3f c0 lis r9,16320
8b4: 38 00 00 05 li r0,5
8b8: 98 09 01 cf stb r0,463(r9)
..\src\FESC_src\/FESC_5554_FSPI.c:18
}
8bc: 81 61 00 00 lwz r11,0(r1)
8c0: 83 eb ff fc lwz r31,-4(r11)
8c4: 7d 61 5b 78 mr r1,r11
8c8: 4e 80 00 20 blr
000008cc <FPGA_SPI_ready_send>:
FPGA_SPI_ready_send():
..\src\FESC_src\/FESC_5554_FSPI.c:21
uint8_t FPGA_SPI_ready_send(uint8_t ch)
{
8cc: 94 21 ff e0 stwu r1,-32(r1)
8d0: 93 e1 00 1c stw r31,28(r1)
8d4: 7c 3f 0b 78 mr r31,r1
8d8: 7c 60 1b 78 mr r0,r3
8dc: 98 1f 00 08 stb r0,8(r31)
..\src\FESC_src\/FESC_5554_FSPI.c:22
if(SXC.CH[ch].SXC_SR.B.BUSY==0) return(1);
8e0: 3d 20 3f c0 lis r9,16320
8e4: 88 1f 00 08 lbz r0,8(r31)
8e8: 54 00 06 3e clrlwi r0,r0,24
8ec: 54 00 30 32 rlwinm r0,r0,6,0,25
8f0: 7d 20 4a 14 add r9,r0,r9
8f4: 88 09 00 07 lbz r0,7(r9)
8f8: 54 00 df fe rlwinm r0,r0,27,31,31
8fc: 2f 80 00 00 cmpwi cr7,r0,0
900: 40 9e 00 10 bne- cr7,910 <TSIZ_256M+0x10>
904: 38 00 00 01 li r0,1
908: 90 1f 00 0c stw r0,12(r31)
90c: 48 00 00 0c b 918 <TSIZ_256M+0x18>
..\src\FESC_src\/FESC_5554_FSPI.c:23
else return(0);
910: 38 00 00 00 li r0,0
914: 90 1f 00 0c stw r0,12(r31)
..\src\FESC_src\/FESC_5554_FSPI.c:24
}
918: 80 7f 00 0c lwz r3,12(r31)
91c: 81 61 00 00 lwz r11,0(r1)
920: 83 eb ff fc lwz r31,-4(r11)
924: 7d 61 5b 78 mr r1,r11
928: 4e 80 00 20 blr
0000092c <FPGA_SPI_ready_read>:
FPGA_SPI_ready_read():
..\src\FESC_src\/FESC_5554_FSPI.c:26
uint8_t FPGA_SPI_ready_read(uint8_t ch)
{
92c: 94 21 ff e0 stwu r1,-32(r1)
930: 93 e1 00 1c stw r31,28(r1)
934: 7c 3f 0b 78 mr r31,r1
938: 7c 60 1b 78 mr r0,r3
93c: 98 1f 00 08 stb r0,8(r31)
..\src\FESC_src\/FESC_5554_FSPI.c:27
if(SXC.CH[ch].SXC_SR.B.RDF==1) return(1);
940: 3d 20 3f c0 lis r9,16320
944: 88 1f 00 08 lbz r0,8(r31)
948: 54 00 06 3e clrlwi r0,r0,24
94c: 54 00 30 32 rlwinm r0,r0,6,0,25
950: 7d 20 4a 14 add r9,r0,r9
954: 88 09 00 07 lbz r0,7(r9)
958: 54 00 d7 fe rlwinm r0,r0,26,31,31
95c: 2f 80 00 01 cmpwi cr7,r0,1
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -