📄 flash.dis
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.\flash.elf: file format elf32-powerpc
Disassembly of section .rcw:
00000000 <.rcw>:
0: 00 5a 00 00 .long 0x5a0000
4: 00 00 76 80 .long 0x7680
Disassembly of section .text:
00000008 <pad_func_config>:
pad_func_config():
..\src\FESC_src\/FESC_5554_general.c:2
void pad_func_config( uint16_t port, uint16_t config)
{
8: 94 21 ff e0 stwu r1,-32(r1)
c: 93 e1 00 1c stw r31,28(r1)
10: 7c 3f 0b 78 mr r31,r1
14: 7c 60 1b 78 mr r0,r3
18: 7c 89 23 78 mr r9,r4
1c: b0 1f 00 08 sth r0,8(r31)
20: 7d 20 4b 78 mr r0,r9
24: b0 1f 00 0a sth r0,10(r31)
..\src\FESC_src\/FESC_5554_general.c:3
SIU.PCR[port].R = config;
28: 3d 20 c3 f9 lis r9,-15367
2c: a0 1f 00 08 lhz r0,8(r31)
30: 54 00 04 3e clrlwi r0,r0,16
34: 54 00 08 3c rlwinm r0,r0,1,0,30
38: 7d 20 4a 14 add r9,r0,r9
3c: 39 29 00 40 addi r9,r9,64
40: a0 1f 00 0a lhz r0,10(r31)
44: b0 09 00 00 sth r0,0(r9)
..\src\FESC_src\/FESC_5554_general.c:4
}
48: 81 61 00 00 lwz r11,0(r1)
4c: 83 eb ff fc lwz r31,-4(r11)
50: 7d 61 5b 78 mr r1,r11
54: 4e 80 00 20 blr
00000058 <set_GPIO>:
set_GPIO():
..\src\FESC_src\/FESC_5554_general.c:10
/*================================================*/
/* GPIO */
/*================================================*/
void set_GPIO(uint8_t pin,uint8_t val)
{
58: 94 21 ff e0 stwu r1,-32(r1)
5c: 93 e1 00 1c stw r31,28(r1)
60: 7c 3f 0b 78 mr r31,r1
64: 7c 60 1b 78 mr r0,r3
68: 7c 89 23 78 mr r9,r4
6c: 98 1f 00 08 stb r0,8(r31)
70: 7d 20 4b 78 mr r0,r9
74: 98 1f 00 09 stb r0,9(r31)
..\src\FESC_src\/FESC_5554_general.c:11
if( val > 1) //toggle PIN
78: 88 1f 00 09 lbz r0,9(r31)
7c: 54 00 06 3e clrlwi r0,r0,24
80: 2b 80 00 01 cmplwi cr7,r0,1
84: 40 9d 00 40 ble- cr7,c4 <DPFEN_ANY+0x4>
..\src\FESC_src\/FESC_5554_general.c:12
SIU.GPDO[pin].R = !SIU.GPDO[pin].R; /* Invert gpio port */
88: 3d 20 c3 f9 lis r9,-15367
8c: 88 1f 00 08 lbz r0,8(r31)
90: 54 00 06 3e clrlwi r0,r0,24
94: 7d 69 02 14 add r11,r9,r0
98: 3d 20 c3 f9 lis r9,-15367
9c: 88 1f 00 08 lbz r0,8(r31)
a0: 54 00 06 3e clrlwi r0,r0,24
a4: 7d 29 02 14 add r9,r9,r0
a8: 88 09 06 00 lbz r0,1536(r9)
ac: 54 00 06 3e clrlwi r0,r0,24
b0: 2f 80 00 00 cmpwi cr7,r0,0
b4: 7c 00 00 26 mfcr r0
b8: 54 00 ff fe rlwinm r0,r0,31,31,31
bc: 98 0b 06 00 stb r0,1536(r11)
c0: 48 00 00 1c b dc <DPFEN_ANY+0x1c>
..\src\FESC_src\/FESC_5554_general.c:14
else
SIU.GPDO[pin].R = val;
c4: 3d 20 c3 f9 lis r9,-15367
c8: 88 1f 00 08 lbz r0,8(r31)
cc: 54 00 06 3e clrlwi r0,r0,24
d0: 7d 29 02 14 add r9,r9,r0
d4: 88 1f 00 09 lbz r0,9(r31)
d8: 98 09 06 00 stb r0,1536(r9)
..\src\FESC_src\/FESC_5554_general.c:15
}
dc: 81 61 00 00 lwz r11,0(r1)
e0: 83 eb ff fc lwz r31,-4(r11)
e4: 7d 61 5b 78 mr r1,r11
e8: 4e 80 00 20 blr
000000ec <set_led>:
set_led():
..\src\FESC_src\/FESC_5554_general.c:18
/*================================================*/
void set_led(uint8_t led, uint8_t status)
{
ec: 94 21 ff e0 stwu r1,-32(r1)
f0: 7c 08 02 a6 mflr r0
f4: 93 e1 00 1c stw r31,28(r1)
f8: 90 01 00 24 stw r0,36(r1)
fc: 7c 3f 0b 78 mr r31,r1
100: 7c 60 1b 78 mr r0,r3
104: 7c 89 23 78 mr r9,r4
108: 98 1f 00 08 stb r0,8(r31)
10c: 7d 20 4b 78 mr r0,r9
110: 98 1f 00 09 stb r0,9(r31)
..\src\FESC_src\/FESC_5554_general.c:19
set_GPIO(led,status);
114: 88 1f 00 08 lbz r0,8(r31)
118: 54 09 06 3e clrlwi r9,r0,24
11c: 88 1f 00 09 lbz r0,9(r31)
120: 54 00 06 3e clrlwi r0,r0,24
124: 7d 23 4b 78 mr r3,r9
128: 7c 04 03 78 mr r4,r0
12c: 4b ff ff 2d bl 58 <set_GPIO>
..\src\FESC_src\/FESC_5554_general.c:20
}
130: 81 61 00 00 lwz r11,0(r1)
134: 80 0b 00 04 lwz r0,4(r11)
138: 7c 08 03 a6 mtlr r0
13c: 83 eb ff fc lwz r31,-4(r11)
140: 7d 61 5b 78 mr r1,r11
144: 4e 80 00 20 blr
00000148 <delay>:
delay():
..\src\FESC_src\/FESC_5554_general.c:30
/*************************************************************************/
/* FUNCTION : delay */
/* PURPOSE : */
/* INPUT NOTES : */
/* RETURN NOTES : None */
/* WARNING : None */
/*************************************************************************/
void delay(uint32_t cnt)
{
148: 94 21 ff e0 stwu r1,-32(r1)
14c: 93 e1 00 1c stw r31,28(r1)
150: 7c 3f 0b 78 mr r31,r1
154: 90 7f 00 08 stw r3,8(r31)
..\src\FESC_src\/FESC_5554_general.c:31
uint32_t i=0;
158: 38 00 00 00 li r0,0
15c: 90 1f 00 0c stw r0,12(r31)
..\src\FESC_src\/FESC_5554_general.c:32
while(i<cnt) i++;
160: 80 1f 00 0c lwz r0,12(r31)
164: 81 3f 00 08 lwz r9,8(r31)
168: 7f 80 48 40 cmplw cr7,r0,r9
16c: 40 9c 00 14 bge- cr7,180 <delay+0x38>
170: 81 3f 00 0c lwz r9,12(r31)
174: 38 09 00 01 addi r0,r9,1
178: 90 1f 00 0c stw r0,12(r31)
17c: 4b ff ff e4 b 160 <delay+0x18>
..\src\FESC_src\/FESC_5554_general.c:33
}
180: 81 61 00 00 lwz r11,0(r1)
184: 83 eb ff fc lwz r31,-4(r11)
188: 7d 61 5b 78 mr r1,r11
18c: 4e 80 00 20 blr
00000190 <char2num>:
char2num():
..\src\FESC_src\/FESC_5554_general.c:43
/*************************************************************************/
/* FUNCTION : char2num */
/* PURPOSE : conv a character to number */
/* INPUT NOTES : */
/* RETURN NOTES : None */
/* WARNING : for char not in ‘0123456789abcdefABCDEF', return0 */
/*************************************************************************/
uint8_t char2num(uint8_t inch)
{
190: 94 21 ff e0 stwu r1,-32(r1)
194: 93 e1 00 1c stw r31,28(r1)
198: 7c 3f 0b 78 mr r31,r1
19c: 7c 60 1b 78 mr r0,r3
1a0: 98 1f 00 08 stb r0,8(r31)
..\src\FESC_src\/FESC_5554_general.c:45
uint8_t ch;
ch = toupper(inch);
1a4: 88 1f 00 08 lbz r0,8(r31)
1a8: 54 00 06 3e clrlwi r0,r0,24
1ac: 90 1f 00 0c stw r0,12(r31)
1b0: 81 3f 00 0c lwz r9,12(r31)
1b4: 91 3f 00 14 stw r9,20(r31)
1b8: 81 7f 00 0c lwz r11,12(r31)
1bc: 3d 20 00 01 lis r9,1
1c0: 38 09 84 e1 addi r0,r9,-31519
1c4: 7d 2b 02 14 add r9,r11,r0
1c8: 88 09 00 00 lbz r0,0(r9)
1cc: 54 00 06 3e clrlwi r0,r0,24
1d0: 54 00 07 bc rlwinm r0,r0,0,30,30
1d4: 2f 80 00 00 cmpwi cr7,r0,0
1d8: 41 9e 00 10 beq- cr7,1e8 <char2num+0x58>
1dc: 81 3f 00 14 lwz r9,20(r31)
1e0: 39 29 ff e0 addi r9,r9,-32
1e4: 91 3f 00 14 stw r9,20(r31)
1e8: 81 3f 00 14 lwz r9,20(r31)
1ec: 7d 20 4b 78 mr r0,r9
1f0: 98 1f 00 09 stb r0,9(r31)
..\src\FESC_src\/FESC_5554_general.c:46
if (( ch <= '9') && (ch >= '0')) return(ch-'0');
1f4: 88 1f 00 09 lbz r0,9(r31)
1f8: 54 00 06 3e clrlwi r0,r0,24
1fc: 2b 80 00 39 cmplwi cr7,r0,57
200: 41 9d 00 28 bgt- cr7,228 <INT_SRAM_128BYTSEGS+0x28>
204: 88 1f 00 09 lbz r0,9(r31)
208: 54 00 06 3e clrlwi r0,r0,24
20c: 2b 80 00 2f cmplwi cr7,r0,47
210: 40 9d 00 18 ble- cr7,228 <INT_SRAM_128BYTSEGS+0x28>
214: 89 3f 00 09 lbz r9,9(r31)
218: 38 09 ff d0 addi r0,r9,-48
21c: 54 00 06 3e clrlwi r0,r0,24
220: 90 1f 00 10 stw r0,16(r31)
224: 48 00 00 40 b 264 <INT_SRAM_128BYTSEGS+0x64>
..\src\FESC_src\/FESC_5554_general.c:47
else if (( ch <= 'F') && (ch >= 'A')) return(ch-'A'+10);
228: 88 1f 00 09 lbz r0,9(r31)
22c: 54 00 06 3e clrlwi r0,r0,24
230: 2b 80 00 46 cmplwi cr7,r0,70
234: 41 9d 00 28 bgt- cr7,25c <INT_SRAM_128BYTSEGS+0x5c>
238: 88 1f 00 09 lbz r0,9(r31)
23c: 54 00 06 3e clrlwi r0,r0,24
240: 2b 80 00 40 cmplwi cr7,r0,64
244: 40 9d 00 18 ble- cr7,25c <INT_SRAM_128BYTSEGS+0x5c>
248: 89 3f 00 09 lbz r9,9(r31)
24c: 38 09 ff c9 addi r0,r9,-55
250: 54 00 06 3e clrlwi r0,r0,24
254: 90 1f 00 10 stw r0,16(r31)
258: 48 00 00 0c b 264 <INT_SRAM_128BYTSEGS+0x64>
..\src\FESC_src\/FESC_5554_general.c:48
else return(0);
25c: 38 00 00 00 li r0,0
260: 90 1f 00 10 stw r0,16(r31)
..\src\FESC_src\/FESC_5554_general.c:49
}
264: 80 7f 00 10 lwz r3,16(r31)
268: 81 61 00 00 lwz r11,0(r1)
26c: 83 eb ff fc lwz r31,-4(r11)
270: 7d 61 5b 78 mr r1,r11
274: 4e 80 00 20 blr
00000278 <init_dpb>:
init_dpb():
..\src\FESC_src\/FESC_5554_general.c:67
/*-----------------------------------------------*/
/* Dual-Port buffer */
/* one routine pushs data into DPB */
/* another routine pops data from it and process */
/* it loSBP_RTSTUS_OKs like a FIFO, dual-port access */
/*-----------------------------------------------*/
/*************************************************************************/
/* FUNCTION : Flush_DP_Buf */
/* PURPOSE : */
/* INPUT NOTES : */
/* RETURN NOTES : None */
/* WARNING : None */
/*************************************************************************/
void init_dpb(DP_BUF_tag* pt,uint8_t* mem,uint32_t len)
{ uint32_t i;
278: 94 21 ff e0 stwu r1,-32(r1)
27c: 93 e1 00 1c stw r31,28(r1)
280: 7c 3f 0b 78 mr r31,r1
284: 90 7f 00 08 stw r3,8(r31)
288: 90 9f 00 0c stw r4,12(r31)
28c: 90 bf 00 10 stw r5,16(r31)
..\src\FESC_src\/FESC_5554_general.c:68
pt->n = 0;
290: 81 3f 00 08 lwz r9,8(r31)
294: 38 00 00 00 li r0,0
298: 90 09 00 00 stw r0,0(r9)
..\src\FESC_src\/FESC_5554_general.c:69
pt->in_n = 0;
29c: 81 3f 00 08 lwz r9,8(r31)
2a0: 38 00 00 00 li r0,0
2a4: 90 09 00 04 stw r0,4(r9)
..\src\FESC_src\/FESC_5554_general.c:70
pt->out_n= 0;
2a8: 81 3f 00 08 lwz r9,8(r31)
2ac: 38 00 00 00 li r0,0
2b0: 90 09 00 08 stw r0,8(r9)
..\src\FESC_src\/FESC_5554_general.c:71
pt->len = len;
2b4: 81 3f 00 08 lwz r9,8(r31)
2b8: 80 1f 00 10 lwz r0,16(r31)
2bc: 90 09 00 0c stw r0,12(r9)
..\src\FESC_src\/FESC_5554_general.c:72
pt->addr = mem;
2c0: 81 3f 00 08 lwz r9,8(r31)
2c4: 80 1f 00 0c lwz r0,12(r31)
2c8: 90 09 00 10 stw r0,16(r9)
..\src\FESC_src\/FESC_5554_general.c:73
for(i=0;i<len;i++) *(mem+i) = 0;
2cc: 38 00 00 00 li r0,0
2d0: 90 1f 00 14 stw r0,20(r31)
2d4: 80 1f 00 14 lwz r0,20(r31)
2d8: 81 3f 00 10 lwz r9,16(r31)
2dc: 7f 80 48 40 cmplw cr7,r0,r9
2e0: 40 9c 00 28 bge- cr7,308 <RWSC_3+0x8>
2e4: 81 3f 00 14 lwz r9,20(r31)
2e8: 80 1f 00 0c lwz r0,12(r31)
2ec: 7d 29 02 14 add r9,r9,r0
2f0: 38 00 00 00 li r0,0
2f4: 98 09 00 00 stb r0,0(r9)
2f8: 81 3f 00 14 lwz r9,20(r31)
2fc: 38 09 00 01 addi r0,r9,1
300: 90 1f 00 14 stw r0,20(r31)
304: 4b ff ff d0 b 2d4 <init_dpb+0x5c>
..\src\FESC_src\/FESC_5554_general.c:74
}
308: 81 61 00 00 lwz r11,0(r1)
30c: 83 eb ff fc lwz r31,-4(r11)
310: 7d 61 5b 78 mr r1,r11
314: 4e 80 00 20 blr
00000318 <push_dpb_data>:
push_dpb_data():
..\src\FESC_src\/FESC_5554_general.c:83
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