📄 flash.lst
字号:
106 00d0 38A00000 li %r7,0
107 00d4 38C00040 li %r8,0
108 00d8 38E00000 li %r9,0
109 00dc 39000000 li %r10,0
110 00e0 39200000 bl cfg_PCR_DATA
111 00e4 39400000 .loc 1 142 0
112 00e8 48000001 li %r0,0
138:..\src/mpc5500_ccdcfg.c ****
139:..\src/mpc5500_ccdcfg.c **** /* This function configures the Pad Configuration Registers (PCR's) for DATA[16:31] */
140:..\src/mpc5500_ccdcfg.c **** /* This function call is not needed for a 16-bit external data bus */
141:..\src/mpc5500_ccdcfg.c **** if(I_DATA_PORT_SIZE == 32) {
142:..\src/mpc5500_ccdcfg.c **** cfg_PCR_DATA(PA_DH, OBE_DH, IBE_DH, DSC_DH, ODE_DH, HYS_DH, SRC_DH, WPE_DH, WPS_DH, DATA_BYT_LS
113 )
114 00ec 38000000 li %r0,16
115 00f0 90010008 stw %r0,12(%r1)
116 00f4 38000010 li %r3,1024
117 00f8 9001000C li %r4,0
118 00fc 38600400 li %r5,0
119 0100 38800000 li %r6,64
120 0104 38A00000 li %r7,0
121 0108 38C00040 li %r8,0
122 010c 38E00000 li %r9,0
123 0110 39000000 li %r10,0
124 0114 39200000 bl cfg_PCR_DATA
125 0118 39400000 .loc 1 146 0
126 011c 48000001 li %r0,0
143:..\src/mpc5500_ccdcfg.c **** }
144:..\src/mpc5500_ccdcfg.c ****
145:..\src/mpc5500_ccdcfg.c **** /* This function configures the Pad Configuration Registers (PCR's) for Control */
146:..\src/mpc5500_ccdcfg.c **** cfg_PCR_CTRL(PA_C1, OBE_C1, IBE_C1, DSC_C1, ODE_C1, HYS_C1, SRC_C1, WPE_C1, WPS_C1, FRST_PCR_CG
127 )
128 0120 38000000 li %r0,62
129 0124 90010008 stw %r0,12(%r1)
130 0128 3800003E li %r0,2
131 012c 9001000C stw %r0,16(%r1)
132 0130 38000002 li %r3,1024
133 0134 90010010 li %r4,0
134 0138 38600400 li %r5,0
135 013c 38800000 li %r6,64
GAS LISTING E:\sys_temp/cceekcaa.s page 6
136 0140 38A00000 li %r7,0
137 0144 38C00040 li %r8,0
138 0148 38E00000 li %r9,0
139 014c 39000000 li %r10,0
140 0150 39200000 bl cfg_PCR_CTRL
141 0154 39400000 .loc 1 149 0
142 0158 48000001 li %r0,1
147:..\src/mpc5500_ccdcfg.c ****
148:..\src/mpc5500_ccdcfg.c **** /* This function configures the Pad Configuration Registers (PCR's) for Control */
149:..\src/mpc5500_ccdcfg.c **** cfg_PCR_CTRL(PA_C2, OBE_C2, IBE_C2, DSC_C2, ODE_C2, HYS_C2, SRC_C2, WPE_C2, WPS_C2,FRST_PCR_CG2
143 li %r0,64
144 015c 38000001 stw %r0,12(%r1)
145 0160 90010008 li %r0,4
146 0164 38000040 stw %r0,16(%r1)
147 0168 9001000C li %r3,1024
148 016c 38000004 li %r4,0
149 0170 90010010 li %r5,0
150 0174 38600400 li %r6,64
151 0178 38800000 li %r7,0
152 017c 38A00000 li %r8,0
153 0180 38C00040 li %r9,0
154 0184 38E00000 li %r10,2
155 0188 39000000 bl cfg_PCR_CTRL
156 018c 39200000 .loc 1 150 0
157 0190 39400002 li %r0,1
158 0194 48000001 stw %r0,8(%r1)
150:..\src/mpc5500_ccdcfg.c **** cfg_PCR_CTRL(PA_C2, OBE_C2, IBE_C2, DSC_C2, ODE_C2, HYS_C2, SRC_C2, WPE_C2, WPS_C2,FRST_PCR_CG3
159 %r0,12(%r1)
160 0198 38000001 li %r0,2
161 019c 90010008 stw %r0,16(%r1)
162 01a0 38000044 li %r3,1024
163 01a4 9001000C li %r4,0
164 01a8 38000002 li %r5,0
165 01ac 90010010 li %r6,64
166 01b0 38600400 li %r7,0
167 01b4 38800000 li %r8,0
168 01b8 38A00000 li %r9,0
169 01bc 38C00040 li %r10,2
170 01c0 38E00000 bl cfg_PCR_CTRL
171 01c4 39000000 .loc 1 151 0
172 01c8 39200000 li %r0,1
173 01cc 39400002 stw %r0,8(%r1)
174 01d0 48000001 li %r0,0
151:..\src/mpc5500_ccdcfg.c **** cfg_PCR_CTRL(PA_C2, OBE_C2, IBE_C2, DSC_C2, ODE_C2, HYS_C2, SRC_C2, WPE_C2, WPS_C2,FRST_PCR_CG4
175
176 01d4 38000001 li %r0,4
177 01d8 90010008 stw %r0,16(%r1)
178 01dc 38000000 li %r3,1024
179 01e0 9001000C li %r4,0
180 01e4 38000004 li %r5,0
181 01e8 90010010 li %r6,64
182 01ec 38600400 li %r7,0
183 01f0 38800000 li %r8,0
184 01f4 38A00000 li %r9,0
185 01f8 38C00040 li %r10,2
186 01fc 38E00000 bl cfg_PCR_CTRL
187 0200 39000000 .loc 1 153 0
GAS LISTING E:\sys_temp/cceekcaa.s page 7
188 0204 39200000 lwz %r11,0(%r1)
189 0208 39400002 lwz %r0,4(%r11)
190 020c 48000001 mtlr %r0
152:..\src/mpc5500_ccdcfg.c ****
153:..\src/mpc5500_ccdcfg.c **** }
191 11)
192 0210 81610000 mr %r1,%r11
193 0214 800B0004 blr
194 0218 7C0803A6 .LFE4:
195 021c 83EBFFFC .size cfg_PCR, .-cfg_PCR
196 0220 7D615B78 .align 2
197 0224 4E800020 .globl cfg_EBI
198 .type cfg_EBI, @function
199 cfg_EBI:
200 .LFB5:
201 .loc 1 163 0
202 stwu %r1,-16(%r1)
203 .LCFI11:
204 mflr %r0
154:..\src/mpc5500_ccdcfg.c ****
155:..\src/mpc5500_ccdcfg.c **** /*****************************************************************/
156:..\src/mpc5500_ccdcfg.c **** /* FUNCTION : cfg_EBI */
157:..\src/mpc5500_ccdcfg.c **** /* PURPOSE : This function configures the EBI Chip Selects. */
158:..\src/mpc5500_ccdcfg.c **** /* INPUT NOTES : None */
159:..\src/mpc5500_ccdcfg.c **** /* RETURN NOTES : None */
160:..\src/mpc5500_ccdcfg.c **** /* WARNING : None */
161:..\src/mpc5500_ccdcfg.c **** /* ***************************************************************/
162:..\src/mpc5500_ccdcfg.c **** void cfg_EBI()
163:..\src/mpc5500_ccdcfg.c **** {
205 r1)
206 0228 9421FFF0 .LCFI12:
207 stw %r0,20(%r1)
208 022c 7C0802A6 .LCFI13:
209 0230 93E1000C mr %r31,%r1
210 .LCFI14:
211 0234 90010014 .loc 1 165 0
212 li %r3,0
213 0238 7C3F0B78 li %r4,0
214 li %r5,0
164:..\src/mpc5500_ccdcfg.c **** /*This function configures the module before any chip select configuration */
165:..\src/mpc5500_ccdcfg.c **** cfg_EBI_mod(SIZEN_VAL, SIZE_VAL, ACGE_VAL, EXTM_VAL, EARB_VAL, EARP_VAL, MDIS_VAL, DBM_VAL);
215 li %r7,0
216 023c 38600000 li %r8,2048
217 0240 38800000 li %r9,0
218 0244 38A00000 li %r10,0
219 0248 38C00000 bl cfg_EBI_mod
220 024c 38E00000 .loc 1 168 0
221 0250 39000800 li %r3,0
222 0254 39200000 lis %r4,0x3ff8
223 0258 39400000 li %r5,0
224 025c 48000001 li %r6,64
166:..\src/mpc5500_ccdcfg.c ****
167:..\src/mpc5500_ccdcfg.c **** /* This function configures the base register for a CS_0 */
168:..\src/mpc5500_ccdcfg.c **** cfg_CSn_BR(CS_0, CS0_BA, CS0_PS, CS0_BL, CS0_WEBS, CS0_TBDIP, CS0_BI, CS0_V);
225 li %r8,0
226 0260 38600000 li %r9,2
227 0264 3C803FF8 li %r10,1
GAS LISTING E:\sys_temp/cceekcaa.s page 8
228 0268 38A00000 bl cfg_CSn_BR
229 026c 38C00040 .loc 1 172 0
230 0270 38E00000 li %r3,0
231 0274 39000000 lis %r4,0xfff8
232 0278 39200002 li %r5,0
233 027c 39400001 li %r6,0
234 0280 48000001 bl cfg_CSn_OR
169:..\src/mpc5500_ccdcfg.c ****
170:..\src/mpc5500_ccdcfg.c **** /* This function configures the option register for CS_0 */
171:..\src/mpc5500_ccdcfg.c **** /* Chip Select 0 is targeted for external Flash with wait states */
172:..\src/mpc5500_ccdcfg.c **** cfg_CSn_OR(CS_0, CS0_AM, CS0_SCY, CS0_BSCY);
235 5 0
236 0284 38600000 li %r3,1
237 0288 3C80FFF8 lis %r4,0x2000
238 028c 38A00000 li %r5,0
239 0290 38C00000 li %r6,0
240 0294 48000001 li %r7,0
173:..\src/mpc5500_ccdcfg.c ****
174:..\src/mpc5500_ccdcfg.c **** /* This function configures the base register for a CS_1 */
175:..\src/mpc5500_ccdcfg.c **** cfg_CSn_BR(CS_1, CS1_BA, CS1_PS, CS1_BL, CS1_WEBS, CS1_TBDIP, CS1_BI, CS1_V);
241 8,0
242 0298 38600001 li %r9,2
243 029c 3C802000 li %r10,1
244 02a0 38A00000 bl cfg_CSn_BR
245 02a4 38C00000 .loc 1 179 0
246 02a8 38E00000 li %r3,1
247 02ac 39000000 lis %r4,0xfff8
248 02b0 39200002 li %r5,0
249 02b4 39400001 li %r6,0
250 02b8 48000001 bl cfg_CSn_OR
176:..\src/mpc5500_ccdcfg.c ****
177:..\src/mpc5500_ccdcfg.c **** /* This function configures the option register for CS_1 */
178:..\src/mpc5500_ccdcfg.c **** /* Chip Select 1 is targeted for external RAM with 4 wait states */
179:..\src/mpc5500_ccdcfg.c **** cfg_CSn_OR(CS_1, CS1_AM, CS1_SCY, CS1_BSCY);
251 2 0
252 02bc 38600001 li %r3,2
253 02c0 3C80FFF8 lis %r4,0x2080
254 02c4 38A00000 li %r5,0
255 02c8 38C00000 li %r6,64
256 02cc 48000001 li %r7,0
180:..\src/mpc5500_ccdcfg.c ****
181:..\src/mpc5500_ccdcfg.c **** /* This function configures the base register for a CS_2 */
182:..\src/mpc5500_ccdcfg.c **** cfg_CSn_BR(CS_2, CS2_BA, CS2_PS, CS2_BL, CS2_WEBS, CS2_TBDIP, CS2_BI, CS2_V);
257 8,0
258 02d0 38600002 li %r9,2
259 02d4 3C802080 li %r10,1
260 02d8 38A00000 bl cfg_CSn_BR
261 02dc 38C00040 .loc 1 186 0
262 02e0 38E00000 li %r3,2
263 02e4 39000000 lis %r4,0xfff8
264 02e8 39200002 li %r5,0
265 02ec 39400001 li %r6,0
266 02f0 48000001 bl cfg_CSn_OR
183:..\src/mpc5500_ccdcfg.c ****
184:..\src/mpc5500_ccdcfg.c **** /* This function configures the option register for CS_2 */
185:..\src/mpc5500_ccdcfg.c **** /* Chip Select 1 is targeted for external RAM with 0 wait states */
186:..\src/mpc5500_ccdcfg.c **** cfg_CSn_OR(CS_2, CS2_AM, CS2_SCY, CS2_BSCY);
GAS LISTING E:\sys_temp/cceekcaa.s page 9
267 9 0
268 02f4 38600002 li %r3,3
269 02f8 3C80FFF8 lis %r4,0x3fc0
270 02fc 38A00000 li %r5,0
271 0300 38C00000 li %r6,64
272 0304 48000001 li %r7,0
187:..\src/mpc5500_ccdcfg.c ****
188:..\src/mpc5500_ccdcfg.c **** /* This function configures the base register for a CS_3 */
189:..\src/mpc5500_ccdcfg.c **** cfg_CSn_BR(CS_3, CS3_BA, CS3_PS, CS3_BL, CS3_WEBS, CS3_TBDIP, CS3_BI, CS3_V);
273 8,0
274 0308 38600003 li %r9,2
275 030c 3C803FC0 li %r10,1
276 0310 38A00000 bl cfg_CSn_BR
277 0314 38C00040 .loc 1 193 0
278 0318 38E00000 li %r3,3
279 031c 39000000 lis %r4,0xfff8
280 0320 39200002 li %r5,32
281 0324 39400001 li %r6,0
282 0328 48000001 bl cfg_CSn_OR
190:..\src/mpc5500_ccdcfg.c ****
191:..\src/mpc5500_ccdcfg.c **** /* This function configures the option register for CS_3 */
192:..\src/mpc5500_ccdcfg.c **** /* Chip Select 1 is targeted for external RAM with 0 wait states */
193:..\src/mpc5500_ccdcfg.c **** cfg_CSn_OR(CS_3, CS3_AM, CS3_SCY, CS3_BSCY);
283 5 0
284 032c 38600003 lwz %r11,0(%r1)
285 0330 3C80FFF8 lwz %r0,4(%r11)
286 0334 38A00020 mtlr %r0
287 0338 38C00000 lwz %r31,-4(%r11)
288 033c 48000001 mr %r1,%r11
194:..\src/mpc5500_ccdcfg.c ****
195:..\src/mpc5500_ccdcfg.c **** } /* End of cfg_EBI */
289 LFE5:
290 0340 81610000 .size cfg_EBI, .-cfg_EBI
291 0344 800B0004 .align 2
292 0348 7C0803A6 .globl cfg_PCR_ADDR
293 034c 83EBFFFC .type cfg_PCR_ADDR, @function
294 0350 7D615B78 cfg_PCR_ADDR:
295 0354 4E800020 .LFB6:
296 .loc 1 215 0
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