📄 ram.dis
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..\src\FESC_src\/FESC_5554_SXC.c:22
||(SXC.CH[brd_no].SELF_WCR.B.CNT != SXC.CH[brd_no].MATE_WCR.B.CNT)
)
{ SBP_Buf[brd_no].returnStat += SBP_RTSTUS_SXC_Veto;
40000d2c: 3d 20 40 01 lis r9,16385
40000d30: 39 29 8e 4c addi r9,r9,-29108
40000d34: 88 1f 00 08 lbz r0,8(r31)
40000d38: 54 00 06 3e clrlwi r0,r0,24
40000d3c: 1c 00 02 24 mulli r0,r0,548
40000d40: 7d 20 4a 14 add r9,r0,r9
40000d44: 39 69 02 10 addi r11,r9,528
40000d48: 3d 20 40 01 lis r9,16385
40000d4c: 39 29 8e 4c addi r9,r9,-29108
40000d50: 88 1f 00 08 lbz r0,8(r31)
40000d54: 54 00 06 3e clrlwi r0,r0,24
40000d58: 1c 00 02 24 mulli r0,r0,548
40000d5c: 7d 20 4a 14 add r9,r0,r9
40000d60: 39 29 02 10 addi r9,r9,528
40000d64: 89 29 00 08 lbz r9,8(r9)
40000d68: 38 09 00 64 addi r0,r9,100
40000d6c: 98 0b 00 08 stb r0,8(r11)
..\src\FESC_src\/FESC_5554_SXC.c:24
//--------- for slave debugging ------
if(SBP_debug_info[brd_no] & REPORT_SLAVE_FAIL)
40000d70: 3d 20 40 01 lis r9,16385
40000d74: 39 29 9f 74 addi r9,r9,-24716
40000d78: 88 1f 00 08 lbz r0,8(r31)
40000d7c: 54 00 06 3e clrlwi r0,r0,24
40000d80: 7d 20 4a 14 add r9,r0,r9
40000d84: 88 09 00 00 lbz r0,0(r9)
40000d88: 54 00 06 3e clrlwi r0,r0,24
40000d8c: 54 00 07 38 rlwinm r0,r0,0,28,28
40000d90: 2f 80 00 00 cmpwi cr7,r0,0
40000d94: 41 9e 00 28 beq- cr7,40000dbc <SXC_master_verify+0x20c>
..\src\FESC_src\/FESC_5554_SXC.c:25
{ printp(send_c_ESCIA_dpb,"IOC板同步有问题！\n\r");
40000d98: 3d 20 40 00 lis r9,16384
40000d9c: 38 69 24 34 addi r3,r9,9268
40000da0: 3d 20 40 00 lis r9,16384
40000da4: 38 89 7b dc addi r4,r9,31708
40000da8: 48 00 0c 6d bl 40001a14 <printp>
..\src\FESC_src\/FESC_5554_SXC.c:26
dump_SXC_CH_info(brd_no);
40000dac: 88 1f 00 08 lbz r0,8(r31)
40000db0: 54 00 06 3e clrlwi r0,r0,24
40000db4: 7c 03 03 78 mr r3,r0
40000db8: 48 00 00 1d bl 40000dd4 <dump_SXC_CH_info>
..\src\FESC_src\/FESC_5554_SXC.c:29
}
}
}
40000dbc: 81 61 00 00 lwz r11,0(r1)
40000dc0: 80 0b 00 04 lwz r0,4(r11)
40000dc4: 7c 08 03 a6 mtlr r0
40000dc8: 83 eb ff fc lwz r31,-4(r11)
40000dcc: 7d 61 5b 78 mr r1,r11
40000dd0: 4e 80 00 20 blr
40000dd4 <dump_SXC_CH_info>:
dump_SXC_CH_info():
..\src\FESC_src\/FESC_5554_SXC.c:36
/******************************************/
/* @2 */
/* ---------------------- */
/* */
/******************************************/
void dump_SXC_CH_info(uint8_t brd_no)
{
40000dd4: 94 21 ff c0 stwu r1,-64(r1)
40000dd8: 7c 08 02 a6 mflr r0
40000ddc: 93 61 00 2c stw r27,44(r1)
40000de0: 93 81 00 30 stw r28,48(r1)
40000de4: 93 a1 00 34 stw r29,52(r1)
40000de8: 93 e1 00 3c stw r31,60(r1)
40000dec: 90 01 00 44 stw r0,68(r1)
40000df0: 7c 3f 0b 78 mr r31,r1
40000df4: 7c 60 1b 78 mr r0,r3
40000df8: 98 1f 00 20 stb r0,32(r31)
..\src\FESC_src\/FESC_5554_SXC.c:37
printp(send_c_ESCIA_dpb,"SXC info: B%d[%s] %d [SELF:%02X %02x %02X %02X] [MATE:%02X %02x %02X %02X]\n\r",
40000dfc: 88 1f 00 20 lbz r0,32(r31)
40000e00: 54 0b 06 3e clrlwi r11,r0,24
40000e04: 3d 20 40 01 lis r9,16385
40000e08: 39 29 8d e0 addi r9,r9,-29216
40000e0c: 88 1f 00 20 lbz r0,32(r31)
40000e10: 54 00 06 3e clrlwi r0,r0,24
40000e14: 54 00 10 3a rlwinm r0,r0,2,0,29
40000e18: 7d 40 4a 14 add r10,r0,r9
40000e1c: 3d 20 3f c0 lis r9,16320
40000e20: 88 1f 00 20 lbz r0,32(r31)
40000e24: 54 00 06 3e clrlwi r0,r0,24
40000e28: 54 00 30 32 rlwinm r0,r0,6,0,25
40000e2c: 7d 20 4a 14 add r9,r0,r9
40000e30: 39 29 00 04 addi r9,r9,4
40000e34: 80 09 00 00 lwz r0,0(r9)
40000e38: 54 00 06 3e clrlwi r0,r0,24
40000e3c: 54 08 07 be clrlwi r8,r0,30
40000e40: 3d 20 3f c0 lis r9,16320
40000e44: 88 1f 00 20 lbz r0,32(r31)
40000e48: 54 00 06 3e clrlwi r0,r0,24
40000e4c: 54 00 30 32 rlwinm r0,r0,6,0,25
40000e50: 7d 20 4a 14 add r9,r0,r9
40000e54: 39 29 00 20 addi r9,r9,32
40000e58: 88 09 00 03 lbz r0,3(r9)
40000e5c: 54 1d 06 3e clrlwi r29,r0,24
40000e60: 3d 20 3f c0 lis r9,16320
40000e64: 88 1f 00 20 lbz r0,32(r31)
40000e68: 54 00 06 3e clrlwi r0,r0,24
40000e6c: 54 00 30 32 rlwinm r0,r0,6,0,25
40000e70: 7d 20 4a 14 add r9,r0,r9
40000e74: 39 29 00 20 addi r9,r9,32
40000e78: 88 09 00 07 lbz r0,7(r9)
40000e7c: 54 1c 06 3e clrlwi r28,r0,24
40000e80: 3d 20 3f c0 lis r9,16320
40000e84: 88 1f 00 20 lbz r0,32(r31)
40000e88: 54 00 06 3e clrlwi r0,r0,24
40000e8c: 54 00 30 32 rlwinm r0,r0,6,0,25
40000e90: 7d 20 4a 14 add r9,r0,r9
40000e94: 39 29 00 20 addi r9,r9,32
40000e98: 88 09 00 0b lbz r0,11(r9)
40000e9c: 54 1b 06 3e clrlwi r27,r0,24
40000ea0: 3d 20 3f c0 lis r9,16320
40000ea4: 88 1f 00 20 lbz r0,32(r31)
40000ea8: 54 00 06 3e clrlwi r0,r0,24
40000eac: 54 00 30 32 rlwinm r0,r0,6,0,25
40000eb0: 7d 20 4a 14 add r9,r0,r9
40000eb4: 39 29 00 20 addi r9,r9,32
40000eb8: 88 09 00 0f lbz r0,15(r9)
40000ebc: 54 00 06 3e clrlwi r0,r0,24
40000ec0: 90 01 00 08 stw r0,8(r1)
40000ec4: 3d 20 3f c0 lis r9,16320
40000ec8: 88 1f 00 20 lbz r0,32(r31)
40000ecc: 54 00 06 3e clrlwi r0,r0,24
40000ed0: 54 00 30 32 rlwinm r0,r0,6,0,25
40000ed4: 7d 20 4a 14 add r9,r0,r9
40000ed8: 39 29 00 30 addi r9,r9,48
40000edc: 88 09 00 03 lbz r0,3(r9)
40000ee0: 54 00 06 3e clrlwi r0,r0,24
40000ee4: 90 01 00 0c stw r0,12(r1)
40000ee8: 3d 20 3f c0 lis r9,16320
40000eec: 88 1f 00 20 lbz r0,32(r31)
40000ef0: 54 00 06 3e clrlwi r0,r0,24
40000ef4: 54 00 30 32 rlwinm r0,r0,6,0,25
40000ef8: 7d 20 4a 14 add r9,r0,r9
40000efc: 39 29 00 30 addi r9,r9,48
40000f00: 88 09 00 07 lbz r0,7(r9)
40000f04: 54 00 06 3e clrlwi r0,r0,24
40000f08: 90 01 00 10 stw r0,16(r1)
40000f0c: 3d 20 3f c0 lis r9,16320
40000f10: 88 1f 00 20 lbz r0,32(r31)
40000f14: 54 00 06 3e clrlwi r0,r0,24
40000f18: 54 00 30 32 rlwinm r0,r0,6,0,25
40000f1c: 7d 20 4a 14 add r9,r0,r9
40000f20: 39 29 00 30 addi r9,r9,48
40000f24: 88 09 00 0b lbz r0,11(r9)
40000f28: 54 00 06 3e clrlwi r0,r0,24
40000f2c: 90 01 00 14 stw r0,20(r1)
40000f30: 3d 20 3f c0 lis r9,16320
40000f34: 88 1f 00 20 lbz r0,32(r31)
40000f38: 54 00 06 3e clrlwi r0,r0,24
40000f3c: 54 00 30 32 rlwinm r0,r0,6,0,25
40000f40: 7d 20 4a 14 add r9,r0,r9
40000f44: 39 29 00 30 addi r9,r9,48
40000f48: 88 09 00 0f lbz r0,15(r9)
40000f4c: 54 00 06 3e clrlwi r0,r0,24
40000f50: 90 01 00 18 stw r0,24(r1)
40000f54: 3d 20 40 00 lis r9,16384
40000f58: 38 69 24 34 addi r3,r9,9268
40000f5c: 3d 20 40 00 lis r9,16384
40000f60: 38 89 7b f0 addi r4,r9,31728
40000f64: 7d 65 5b 78 mr r5,r11
40000f68: 80 ca 00 00 lwz r6,0(r10)
40000f6c: 7d 07 43 78 mr r7,r8
40000f70: 7f a8 eb 78 mr r8,r29
40000f74: 7f 89 e3 78 mr r9,r28
40000f78: 7f 6a db 78 mr r10,r27
40000f7c: 4c c6 31 82 crclr 4*cr1+eq
40000f80: 48 00 0a 95 bl 40001a14 <printp>
..\src\FESC_src\/FESC_5554_SXC.c:49
brd_no,
board_name[brd_no],
((uint8_t)SXC.CH[brd_no].SXC_SR.R & 0x03),
SXC.CH[brd_no].SELF_PCR.B.CNT,
SXC.CH[brd_no].SELF_WCR.B.CNT,
SXC.CH[brd_no].SELF_OUT_SPY_R.B.DATA,
SXC.CH[brd_no].SELF_IN_SPY_R.B.DATA,
SXC.CH[brd_no].MATE_PCR.B.CNT,
SXC.CH[brd_no].MATE_WCR.B.CNT,
SXC.CH[brd_no].MATE_OUT_SPY_R.B.DATA,
SXC.CH[brd_no].MATE_IN_SPY_R.B.DATA);
}
40000f84: 81 61 00 00 lwz r11,0(r1)
40000f88: 80 0b 00 04 lwz r0,4(r11)
40000f8c: 7c 08 03 a6 mtlr r0
40000f90: 83 6b ff ec lwz r27,-20(r11)
40000f94: 83 8b ff f0 lwz r28,-16(r11)
40000f98: 83 ab ff f4 lwz r29,-12(r11)
40000f9c: 83 eb ff fc lwz r31,-4(r11)
40000fa0: 7d 61 5b 78 mr r1,r11
40000fa4: 4e 80 00 20 blr
40000fa8 <init_SXC>:
init_SXC():
..\src\FESC_src\/FESC_5554_SXC.c:57
/******************************************/
/* @2 */
/* ---------------------- */
/* */
/******************************************/
void init_SXC(void)
{ uint8_t i;
40000fa8: 94 21 ff e0 stwu r1,-32(r1)
40000fac: 93 e1 00 1c stw r31,28(r1)
40000fb0: 7c 3f 0b 78 mr r31,r1
..\src\FESC_src\/FESC_5554_SXC.c:58
for(i=0;i<8;i++)
40000fb4: 38 00 00 00 li r0,0
40000fb8: 98 1f 00 08 stb r0,8(r31)
40000fbc: 88 1f 00 08 lbz r0,8(r31)
40000fc0: 54 00 06 3e clrlwi r0,r0,24
40000fc4: 2b 80 00 07 cmplwi cr7,r0,7
40000fc8: 41 9d 00 34 bgt- cr7,40000ffc <init_SXC+0x54>
..\src\FESC_src\/FESC_5554_SXC.c:60
{
SXC.CH[i].SXC_CR.B.PACKET_CNT_CLR = 1;
40000fcc: 3d 20 3f c0 lis r9,16320
40000fd0: 88 1f 00 08 lbz r0,8(r31)
40000fd4: 54 00 06 3e clrlwi r0,r0,24
40000fd8: 54 00 30 32 rlwinm r0,r0,6,0,25
40000fdc: 7d 20 4a 14 add r9,r0,r9
40000fe0: 88 09 00 03 lbz r0,3(r9)
40000fe4: 60 00 00 02 ori r0,r0,2
40000fe8: 98 09 00 03 stb r0,3(r9)
..\src\FESC_src\/FESC_5554_SXC.c:58
40000fec: 89 3f 00 08 lbz r9,8(r31)
40000ff0: 38 09 00 01 addi r0,r9,1
40000ff4: 98 1f 00 08 stb r0,8(r31)
40000ff8: 4b ff ff c4 b 40000fbc <init_SXC+0x14>
..\src\FESC_src\/FESC_5554_SXC.c:63
//SXC.CH[i].SXC_CR.B.PACKET_START = 1;
}
}
40000ffc: 81 61 00 00 lwz r11,0(r1)
40001000: 83 eb ff fc lwz r31,-4(r11)
40001004: 7d 61 5b 78 mr r1,r11
40001008: 4e 80 00 20 blr
4000100c <init_EMIOS>:
init_EMIOS():
..\src\FESC_src\/FESC_5554_EMIOS.c:23
/* @2 */
/* ---------------------- */
/* */
/******************************************/
void init_EMIOS(void) {
4000100c: 94 21 ff e0 stwu r1,-32(r1)
40001010: 7c 08 02 a6 mflr r0
40001014: 93 e1 00 1c stw r31,28(r1)
40001018: 90 01 00 24 stw r0,36(r1)
4000101c: 7c 3f 0b 78 mr r31,r1
..\src\FESC_src\/FESC_5554_EMIOS.c:25
uint8_t i;
EMIOS.MCR.B.GPRE= 119; /* Divide 120MHz sysclk by 119+1 for 1MHz eMIOS clk*/
40001020: 3d 20 c3 fa lis r9,-15366
40001024: 38 00 00 77 li r0,119
40001028: 98 09 00 02 stb r0,2(r9)
..\src\FESC_src\/FESC_5554_EMIOS.c:27
//EMIOS.MCR.B.GPRE= 127; /* Divide 128MHz sysclk by 127+1 for 1MHz eMIOS clk*/
EMIOS.MCR.B.GPREN = 1; /* Enable eMIOS clock */
4000102c: 3d 20 c3 fa lis r9,-15366
40001030: 88 09 00 00 lbz r0,0(r9)
40001034: 60 00 00 04 ori r0,r0,4
40001038: 98 09 00 00 stb r0,0(r9)
..\src\FESC_src\/FESC_5554_EMIOS.c:28
EMIOS.MCR.B.GTBE = 1; /* Enable global time base */
4000103c: 3d 20 c3 fa lis r9,-15366
40001040: 88 09 00 00 lbz r0,0(r9)
40001044: 60 00 00 10 ori r0,r0,16
40001048: 98 09 00 00 stb r0,0(r9)
..\src\FESC_src\/FESC_5554_EMIOS.c:29
EMIOS.MCR.B.FRZ = 1; /* Enable stopping channels when in debug mode */
4000104c: 3d 20 c3 fa lis r9,-15366
40001050: 88 09 00 00 lbz r0,0(r9)
40001054: 60 00 00 20 ori r0,r0,32
40001058: 98 09 00 00 stb r0,0(r9)
..\src\FESC_src\/FESC_5554_EMIOS.c:31
set_GPIO(PIN_EMIOS2,1);
4000105c: 38 60 00 b5 li r3,181
40001060: 38 80 00 01 li r4,1
40001064: 4b ff ef ed bl 40000050 <set_GPIO>
..\src\FESC_src\/FESC_5554_EMIOS.c:32
set_GPIO(PIN_EMIOS3,1);
40001068: 38 60 00 b6 li r3,182
4000106c: 38 80 00 01 li r4,1
40001070: 4b ff ef e1 bl 40000050 <set_GPIO>
..\src\FESC_src\/FESC_5554_EMIOS.c:33
set_GPIO(PIN_EMIOS4,1);
40001074: 38 60 00 b7 li r3,183
40001078: 38 80 00 01 li r4,1
4000107c: 4b ff ef d5 bl 40000050 <set_GPIO>
..\src\FESC_src\/FESC_5554_EMIOS.c:34
pad_func_config(PIN_EMIOS2,GPIO_FUNCTION | OUTPUT_MODE | DRIVE_STRENGTH_50PF ); //GPIO OUTPUT
40001080: 38 60 00 b5 li r3,181
40001084: 38 80 02 c0 li r4,704
40001088: 4b ff ef 79 bl 40000000 <PEFILL>
..\src\FESC_src\/FESC_5554_EMIOS.c:35
pad_func_config(PIN_EMIOS3,GPIO_FUNCTION | OUTPUT_MODE | DRIVE_STRENGTH_50PF ); //GPIO OUTPUT
4000108c: 38 60 00 b6 li r3,182
40001090: 38 80 02 c0 li r4,704
40001094: 4b ff ef 6d bl 40000000 <PEFILL>
..\src\FESC_src\/FESC_5554_EMIOS.c:36
pad_func_config(PIN_EMIOS4,GPIO_FUNCTION | OUTPUT_MODE | DRIVE_STRENGTH_50PF ); //GPIO OUTPUT
40001098: 38 60 00 b7 li r3,183
4000109c: 38 80 02 c0 li r4,704
400010a0: 4b ff ef 61 bl 40000000 <PEFILL>
..\src\FESC_src\/FESC_5554_EMIOS.c:39
/* Setup EMIOS15-23 as LED control pins */
for(i=0;i<9;i++)
400010a4: 38 00 00 00 li r0,0
400010a8: 98 1f 00 08 stb r0,8(r31)
400010ac: 88 1f 00 08 lbz r0,8(r31)
400010b0: 54 00 06 3e clrlwi r0,r0,24
400010b4: 2b 80 00 08 cmplwi cr7,r0,8
400010b8: 41 9d⌨️ 快捷键说明
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