📄 ram.dis
字号:
40000954: 2f 80 00 01 cmpwi cr7,r0,1
40000958: 40 9e 00 10 bne- cr7,40000968 <FPGA_SPI_ready_read+0x44>
4000095c: 38 00 00 01 li r0,1
40000960: 90 1f 00 0c stw r0,12(r31)
40000964: 48 00 00 0c b 40000970 <FPGA_SPI_ready_read+0x4c>
..\src\FESC_src\/FESC_5554_FSPI.c:28
else return(0);
40000968: 38 00 00 00 li r0,0
4000096c: 90 1f 00 0c stw r0,12(r31)
..\src\FESC_src\/FESC_5554_FSPI.c:29
}
40000970: 80 7f 00 0c lwz r3,12(r31)
40000974: 81 61 00 00 lwz r11,0(r1)
40000978: 83 eb ff fc lwz r31,-4(r11)
4000097c: 7d 61 5b 78 mr r1,r11
40000980: 4e 80 00 20 blr
40000984 <FPGA_SPI_Send>:
FPGA_SPI_Send():
..\src\FESC_src\/FESC_5554_FSPI.c:32
void FPGA_SPI_Send(uint8_t ch,uint8_t TxDATA)
{ SXC.CH[ch].SXC_CR.B.TCFC = 1;
40000984: 94 21 ff e0 stwu r1,-32(r1)
40000988: 93 e1 00 1c stw r31,28(r1)
4000098c: 7c 3f 0b 78 mr r31,r1
40000990: 7c 60 1b 78 mr r0,r3
40000994: 7c 89 23 78 mr r9,r4
40000998: 98 1f 00 08 stb r0,8(r31)
4000099c: 7d 20 4b 78 mr r0,r9
400009a0: 98 1f 00 09 stb r0,9(r31)
400009a4: 3d 20 3f c0 lis r9,16320
400009a8: 88 1f 00 08 lbz r0,8(r31)
400009ac: 54 00 06 3e clrlwi r0,r0,24
400009b0: 54 00 30 32 rlwinm r0,r0,6,0,25
400009b4: 7d 20 4a 14 add r9,r0,r9
400009b8: 88 09 00 03 lbz r0,3(r9)
400009bc: 64 00 ff ff oris r0,r0,65535
400009c0: 60 00 ff 80 ori r0,r0,65408
400009c4: 98 09 00 03 stb r0,3(r9)
..\src\FESC_src\/FESC_5554_FSPI.c:33
SXC.CH[ch].SPI_HOST_DATA_REG.B.DATA = TxDATA;
400009c8: 3d 20 3f c0 lis r9,16320
400009cc: 88 1f 00 08 lbz r0,8(r31)
400009d0: 54 00 06 3e clrlwi r0,r0,24
400009d4: 54 00 30 32 rlwinm r0,r0,6,0,25
400009d8: 7d 20 4a 14 add r9,r0,r9
400009dc: 88 1f 00 09 lbz r0,9(r31)
400009e0: 98 09 00 0b stb r0,11(r9)
..\src\FESC_src\/FESC_5554_FSPI.c:34
SXC.CH[ch].SXC_CR.B.SEND = 1;
400009e4: 3d 20 3f c0 lis r9,16320
400009e8: 88 1f 00 08 lbz r0,8(r31)
400009ec: 54 00 06 3e clrlwi r0,r0,24
400009f0: 54 00 30 32 rlwinm r0,r0,6,0,25
400009f4: 7d 20 4a 14 add r9,r0,r9
400009f8: 88 09 00 03 lbz r0,3(r9)
400009fc: 60 00 00 20 ori r0,r0,32
40000a00: 98 09 00 03 stb r0,3(r9)
..\src\FESC_src\/FESC_5554_FSPI.c:35
}
40000a04: 81 61 00 00 lwz r11,0(r1)
40000a08: 83 eb ff fc lwz r31,-4(r11)
40000a0c: 7d 61 5b 78 mr r1,r11
40000a10: 4e 80 00 20 blr
40000a14 <FPGA_SPI_Read>:
FPGA_SPI_Read():
..\src\FESC_src\/FESC_5554_FSPI.c:37
uint8_t FPGA_SPI_Read(uint8_t ch)
{
40000a14: 94 21 ff e0 stwu r1,-32(r1)
40000a18: 93 e1 00 1c stw r31,28(r1)
40000a1c: 7c 3f 0b 78 mr r31,r1
40000a20: 7c 60 1b 78 mr r0,r3
40000a24: 98 1f 00 08 stb r0,8(r31)
..\src\FESC_src\/FESC_5554_FSPI.c:38
SXC.CH[ch].SXC_CR.B.RDFC = 1;
40000a28: 3d 20 3f c0 lis r9,16320
40000a2c: 88 1f 00 08 lbz r0,8(r31)
40000a30: 54 00 06 3e clrlwi r0,r0,24
40000a34: 54 00 30 32 rlwinm r0,r0,6,0,25
40000a38: 7d 20 4a 14 add r9,r0,r9
40000a3c: 88 09 00 03 lbz r0,3(r9)
40000a40: 60 00 00 40 ori r0,r0,64
40000a44: 98 09 00 03 stb r0,3(r9)
..\src\FESC_src\/FESC_5554_FSPI.c:39
return(SXC.CH[ch].SPI_HOST_DATA_REG.B.DATA);
40000a48: 3d 20 3f c0 lis r9,16320
40000a4c: 88 1f 00 08 lbz r0,8(r31)
40000a50: 54 00 06 3e clrlwi r0,r0,24
40000a54: 54 00 30 32 rlwinm r0,r0,6,0,25
40000a58: 7d 20 4a 14 add r9,r0,r9
40000a5c: 88 09 00 0b lbz r0,11(r9)
40000a60: 54 00 06 3e clrlwi r0,r0,24
40000a64: 54 00 06 3e clrlwi r0,r0,24
..\src\FESC_src\/FESC_5554_FSPI.c:40
}
40000a68: 7c 03 03 78 mr r3,r0
40000a6c: 81 61 00 00 lwz r11,0(r1)
40000a70: 83 eb ff fc lwz r31,-4(r11)
40000a74: 7d 61 5b 78 mr r1,r11
40000a78: 4e 80 00 20 blr
40000a7c <FPGA_SPI_Swap>:
FPGA_SPI_Swap():
..\src\FESC_src\/FESC_5554_FSPI.c:44
uint8_t FPGA_SPI_Swap(uint8_t ch,uint8_t TxDATA)
{
40000a7c: 94 21 ff e0 stwu r1,-32(r1)
40000a80: 93 e1 00 1c stw r31,28(r1)
40000a84: 7c 3f 0b 78 mr r31,r1
40000a88: 7c 60 1b 78 mr r0,r3
40000a8c: 7c 89 23 78 mr r9,r4
40000a90: 98 1f 00 08 stb r0,8(r31)
40000a94: 7d 20 4b 78 mr r0,r9
40000a98: 98 1f 00 09 stb r0,9(r31)
..\src\FESC_src\/FESC_5554_FSPI.c:45
if((SXC.CH[ch].SXC_SR.B.BUSY == 0) && (SXC.CH[3].SXC_SR.B.TCF == 0))
40000a9c: 3d 20 3f c0 lis r9,16320
40000aa0: 88 1f 00 08 lbz r0,8(r31)
40000aa4: 54 00 06 3e clrlwi r0,r0,24
40000aa8: 54 00 30 32 rlwinm r0,r0,6,0,25
40000aac: 7d 20 4a 14 add r9,r0,r9
40000ab0: 88 09 00 07 lbz r0,7(r9)
40000ab4: 54 00 df fe rlwinm r0,r0,27,31,31
40000ab8: 2f 80 00 00 cmpwi cr7,r0,0
40000abc: 40 9e 00 34 bne- cr7,40000af0 <FPGA_SPI_Swap+0x74>
40000ac0: 3d 20 3f c0 lis r9,16320
40000ac4: 88 09 00 c7 lbz r0,199(r9)
40000ac8: 54 00 cf fe rlwinm r0,r0,25,31,31
40000acc: 2f 80 00 00 cmpwi cr7,r0,0
40000ad0: 40 9e 00 20 bne- cr7,40000af0 <FPGA_SPI_Swap+0x74>
..\src\FESC_src\/FESC_5554_FSPI.c:46
SXC.CH[ch].SPI_HOST_DATA_REG.B.DATA = TxDATA;
40000ad4: 3d 20 3f c0 lis r9,16320
40000ad8: 88 1f 00 08 lbz r0,8(r31)
40000adc: 54 00 06 3e clrlwi r0,r0,24
40000ae0: 54 00 30 32 rlwinm r0,r0,6,0,25
40000ae4: 7d 20 4a 14 add r9,r0,r9
40000ae8: 88 1f 00 09 lbz r0,9(r31)
40000aec: 98 09 00 0b stb r0,11(r9)
..\src\FESC_src\/FESC_5554_FSPI.c:47
SXC.CH[ch].SXC_CR.B.SEND = 1;
40000af0: 3d 20 3f c0 lis r9,16320
40000af4: 88 1f 00 08 lbz r0,8(r31)
40000af8: 54 00 06 3e clrlwi r0,r0,24
40000afc: 54 00 30 32 rlwinm r0,r0,6,0,25
40000b00: 7d 20 4a 14 add r9,r0,r9
40000b04: 88 09 00 03 lbz r0,3(r9)
40000b08: 60 00 00 20 ori r0,r0,32
40000b0c: 98 09 00 03 stb r0,3(r9)
..\src\FESC_src\/FESC_5554_FSPI.c:48
while(SXC.CH[ch].SXC_SR.B.BUSY == 1){}
40000b10: 3d 20 3f c0 lis r9,16320
40000b14: 88 1f 00 08 lbz r0,8(r31)
40000b18: 54 00 06 3e clrlwi r0,r0,24
40000b1c: 54 00 30 32 rlwinm r0,r0,6,0,25
40000b20: 7d 20 4a 14 add r9,r0,r9
40000b24: 88 09 00 07 lbz r0,7(r9)
40000b28: 54 00 df fe rlwinm r0,r0,27,31,31
40000b2c: 2f 80 00 01 cmpwi cr7,r0,1
40000b30: 40 9e 00 08 bne- cr7,40000b38 <FPGA_SPI_Swap+0xbc>
40000b34: 4b ff ff dc b 40000b10 <FPGA_SPI_Swap+0x94>
..\src\FESC_src\/FESC_5554_FSPI.c:49
SXC.CH[ch].SXC_CR.B.TCFC = 1;
40000b38: 3d 20 3f c0 lis r9,16320
40000b3c: 88 1f 00 08 lbz r0,8(r31)
40000b40: 54 00 06 3e clrlwi r0,r0,24
40000b44: 54 00 30 32 rlwinm r0,r0,6,0,25
40000b48: 7d 20 4a 14 add r9,r0,r9
40000b4c: 88 09 00 03 lbz r0,3(r9)
40000b50: 64 00 ff ff oris r0,r0,65535
40000b54: 60 00 ff 80 ori r0,r0,65408
40000b58: 98 09 00 03 stb r0,3(r9)
..\src\FESC_src\/FESC_5554_FSPI.c:50
SXC.CH[ch].SXC_CR.B.RDFC = 1;
40000b5c: 3d 20 3f c0 lis r9,16320
40000b60: 88 1f 00 08 lbz r0,8(r31)
40000b64: 54 00 06 3e clrlwi r0,r0,24
40000b68: 54 00 30 32 rlwinm r0,r0,6,0,25
40000b6c: 7d 20 4a 14 add r9,r0,r9
40000b70: 88 09 00 03 lbz r0,3(r9)
40000b74: 60 00 00 40 ori r0,r0,64
40000b78: 98 09 00 03 stb r0,3(r9)
..\src\FESC_src\/FESC_5554_FSPI.c:51
return(SXC.CH[ch].SPI_HOST_DATA_REG.B.DATA);
40000b7c: 3d 20 3f c0 lis r9,16320
40000b80: 88 1f 00 08 lbz r0,8(r31)
40000b84: 54 00 06 3e clrlwi r0,r0,24
40000b88: 54 00 30 32 rlwinm r0,r0,6,0,25
40000b8c: 7d 20 4a 14 add r9,r0,r9
40000b90: 88 09 00 0b lbz r0,11(r9)
40000b94: 54 00 06 3e clrlwi r0,r0,24
40000b98: 54 00 06 3e clrlwi r0,r0,24
..\src\FESC_src\/FESC_5554_FSPI.c:52
}
40000b9c: 7c 03 03 78 mr r3,r0
40000ba0: 81 61 00 00 lwz r11,0(r1)
40000ba4: 83 eb ff fc lwz r31,-4(r11)
40000ba8: 7d 61 5b 78 mr r1,r11
40000bac: 4e 80 00 20 blr
40000bb0 <SXC_master_verify>:
SXC_master_verify():
..\src\FESC_src\/FESC_5554_SXC.c:7
/* ---------------------- */
/* */
/******************************************/
void SXC_master_verify(uint8_t brd_no)
{
40000bb0: 94 21 ff e0 stwu r1,-32(r1)
40000bb4: 7c 08 02 a6 mflr r0
40000bb8: 93 e1 00 1c stw r31,28(r1)
40000bbc: 90 01 00 24 stw r0,36(r1)
40000bc0: 7c 3f 0b 78 mr r31,r1
40000bc4: 7c 60 1b 78 mr r0,r3
40000bc8: 98 1f 00 08 stb r0,8(r31)
..\src\FESC_src\/FESC_5554_SXC.c:8
if( SXC.CH[brd_no].SXC_SR.B.master_fail_first
40000bcc: 3d 20 3f c0 lis r9,16320
40000bd0: 88 1f 00 08 lbz r0,8(r31)
40000bd4: 54 00 06 3e clrlwi r0,r0,24
40000bd8: 54 00 30 32 rlwinm r0,r0,6,0,25
40000bdc: 7d 20 4a 14 add r9,r0,r9
40000be0: 88 09 00 07 lbz r0,7(r9)
40000be4: 54 00 ff fe rlwinm r0,r0,31,31,31
40000be8: 2f 80 00 00 cmpwi cr7,r0,0
40000bec: 40 9e 00 50 bne- cr7,40000c3c <SXC_master_verify+0x8c>
40000bf0: 3d 20 3f c0 lis r9,16320
40000bf4: 88 1f 00 08 lbz r0,8(r31)
40000bf8: 54 00 06 3e clrlwi r0,r0,24
40000bfc: 54 00 30 32 rlwinm r0,r0,6,0,25
40000c00: 7d 20 4a 14 add r9,r0,r9
40000c04: 39 69 00 20 addi r11,r9,32
40000c08: 3d 20 3f c0 lis r9,16320
40000c0c: 88 1f 00 08 lbz r0,8(r31)
40000c10: 54 00 06 3e clrlwi r0,r0,24
40000c14: 54 00 30 32 rlwinm r0,r0,6,0,25
40000c18: 7d 20 4a 14 add r9,r0,r9
40000c1c: 39 29 00 30 addi r9,r9,48
40000c20: 88 0b 00 03 lbz r0,3(r11)
40000c24: 54 0b 06 3e clrlwi r11,r0,24
40000c28: 88 09 00 03 lbz r0,3(r9)
40000c2c: 54 00 06 3e clrlwi r0,r0,24
40000c30: 7f 8b 00 00 cmpw cr7,r11,r0
40000c34: 40 9e 00 08 bne- cr7,40000c3c <SXC_master_verify+0x8c>
40000c38: 48 00 00 84 b 40000cbc <SXC_master_verify+0x10c>
..\src\FESC_src\/FESC_5554_SXC.c:11
||(SXC.CH[brd_no].SELF_PCR.B.CNT != SXC.CH[brd_no].MATE_PCR.B.CNT)
)
{ SBP_Buf[brd_no].returnStat += SBP_RTSTUS_SXC_Veto;
40000c3c: 3d 20 40 01 lis r9,16385
40000c40: 39 29 8e 4c addi r9,r9,-29108
40000c44: 88 1f 00 08 lbz r0,8(r31)
40000c48: 54 00 06 3e clrlwi r0,r0,24
40000c4c: 1c 00 02 24 mulli r0,r0,548
40000c50: 7d 20 4a 14 add r9,r0,r9
40000c54: 39 69 02 10 addi r11,r9,528
40000c58: 3d 20 40 01 lis r9,16385
40000c5c: 39 29 8e 4c addi r9,r9,-29108
40000c60: 88 1f 00 08 lbz r0,8(r31)
40000c64: 54 00 06 3e clrlwi r0,r0,24
40000c68: 1c 00 02 24 mulli r0,r0,548
40000c6c: 7d 20 4a 14 add r9,r0,r9
40000c70: 39 29 02 10 addi r9,r9,528
40000c74: 89 29 00 08 lbz r9,8(r9)
40000c78: 38 09 00 64 addi r0,r9,100
40000c7c: 98 0b 00 08 stb r0,8(r11)
..\src\FESC_src\/FESC_5554_SXC.c:12
dump_SXC_CH_info(brd_no);
40000c80: 88 1f 00 08 lbz r0,8(r31)
40000c84: 54 00 06 3e clrlwi r0,r0,24
40000c88: 7c 03 03 78 mr r3,r0
40000c8c: 48 00 01 49 bl 40000dd4 <dump_SXC_CH_info>
..\src\FESC_src\/FESC_5554_SXC.c:13
dump_SBP_lastPack(brd_no);
40000c90: 88 1f 00 08 lbz r0,8(r31)
40000c94: 54 00 06 3e clrlwi r0,r0,24
40000c98: 7c 03 03 78 mr r3,r0
40000c9c: 48 00 44 bd bl 40005158 <dump_SBP_lastPack>
..\src\FESC_src\/FESC_5554_SXC.c:14
printp(send_c_ESCIA_dpb,"n\r主控制板取2失败\n\r");
40000ca0: 3d 20 40 00 lis r9,16384
40000ca4: 38 69 24 34 addi r3,r9,9268
40000ca8: 3d 20 40 00 lis r9,16384
40000cac: 38 89 7b c8 addi r4,r9,31688
40000cb0: 48 00 0d 65 bl 40001a14 <printp>
..\src\FESC_src\/FESC_5554_SXC.c:16
command_line_interface();
40000cb4: 48 00 4b ed bl 400058a0 <command_line_interface>
..\src\FESC_src\/FESC_5554_SXC.c:17
while(1){}
40000cb8: 48 00 00 00 b 40000cb8 <SXC_master_verify+0x108>
..\src\FESC_src\/FESC_5554_SXC.c:19
}
if( SXC.CH[brd_no].SXC_SR.B.slave_fail_first
40000cbc: 3d 20 3f c0 lis r9,16320
40000cc0: 88 1f 00 08 lbz r0,8(r31)
40000cc4: 54 00 06 3e clrlwi r0,r0,24
40000cc8: 54 00 30 32 rlwinm r0,r0,6,0,25
40000ccc: 7d 20 4a 14 add r9,r0,r9
40000cd0: 88 09 00 07 lbz r0,7(r9)
40000cd4: 54 00 07 fe clrlwi r0,r0,31
40000cd8: 2f 80 00 00 cmpwi cr7,r0,0
40000cdc: 40 9e 00 50 bne- cr7,40000d2c <SXC_master_verify+0x17c>
40000ce0: 3d 20 3f c0 lis r9,16320
40000ce4: 88 1f 00 08 lbz r0,8(r31)
40000ce8: 54 00 06 3e clrlwi r0,r0,24
40000cec: 54 00 30 32 rlwinm r0,r0,6,0,25
40000cf0: 7d 20 4a 14 add r9,r0,r9
40000cf4: 39 69 00 20 addi r11,r9,32
40000cf8: 3d 20 3f c0 lis r9,16320
40000cfc: 88 1f 00 08 lbz r0,8(r31)
40000d00: 54 00 06 3e clrlwi r0,r0,24
40000d04: 54 00 30 32 rlwinm r0,r0,6,0,25
40000d08: 7d 20 4a 14 add r9,r0,r9
40000d0c: 39 29 00 30 addi r9,r9,48
40000d10: 88 0b 00 07 lbz r0,7(r11)
40000d14: 54 0b 06 3e clrlwi r11,r0,24
40000d18: 88 09 00 07 lbz r0,7(r9)
40000d1c: 54 00 06 3e clrlwi r0,r0,24
40000d20: 7f 8b 00 00 cmpw cr7,r11,r0
40000d24: 40 9e 00 08 bne- cr7,40000d2c <SXC_master_verify+0x17c>
40000d28: 48 00 00 94 b 40000dbc <SXC_master_verify+0x20c>
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