📄 ram.dis
字号:
40000620: 38 60 00 5a li r3,90
40000624: 38 80 0c 00 li r4,3072
40000628: 4b ff f9 d9 bl 40000000 <PEFILL>
..\src\FESC_src\/FESC_5554_ESCI.c:19
//ESCI_B.CR1.B.SBR = 781; //
//ESCI_B.CR1.B.TE = 1;
//ESCI_B.CR1.B.RE = 1;
ESCI_B.CR1.R = 0x0187000C;
4000062c: 3d 20 ff fb lis r9,-5
40000630: 61 29 40 00 ori r9,r9,16384
40000634: 3c 00 01 87 lis r0,391
40000638: 60 00 00 0c ori r0,r0,12
4000063c: 90 09 00 00 stw r0,0(r9)
..\src\FESC_src\/FESC_5554_ESCI.c:20
pad_func_config(PIN_TXD_B_GPIO91,PRIMARY_FUNCTION); //SCI
40000640: 38 60 00 5b li r3,91
40000644: 38 80 0c 00 li r4,3072
40000648: 4b ff f9 b9 bl 40000000 <PEFILL>
..\src\FESC_src\/FESC_5554_ESCI.c:21
pad_func_config(PIN_RXD_B_GPIO92,PRIMARY_FUNCTION); //SCI
4000064c: 38 60 00 5c li r3,92
40000650: 38 80 0c 00 li r4,3072
40000654: 4b ff f9 ad bl 40000000 <PEFILL>
..\src\FESC_src\/FESC_5554_ESCI.c:22
}
40000658: 81 61 00 00 lwz r11,0(r1)
4000065c: 80 0b 00 04 lwz r0,4(r11)
40000660: 7c 08 03 a6 mtlr r0
40000664: 83 eb ff fc lwz r31,-4(r11)
40000668: 7d 61 5b 78 mr r1,r11
4000066c: 4e 80 00 20 blr
40000670 <send_c_ESCIA>:
send_c_ESCIA():
..\src\FESC_src\/FESC_5554_ESCI.c:25
void send_c_ESCIA(uint8_t schar)
{
40000670: 94 21 ff e0 stwu r1,-32(r1)
40000674: 93 e1 00 1c stw r31,28(r1)
40000678: 7c 3f 0b 78 mr r31,r1
4000067c: 7c 60 1b 78 mr r0,r3
40000680: 98 1f 00 08 stb r0,8(r31)
..\src\FESC_src\/FESC_5554_ESCI.c:26
while(ESCI_A.SR.B.TDRE ==0) {}
40000684: 3d 20 ff fb lis r9,-5
40000688: 88 09 00 08 lbz r0,8(r9)
4000068c: 54 00 cf fe rlwinm r0,r0,25,31,31
40000690: 2f 80 00 00 cmpwi cr7,r0,0
40000694: 40 9e 00 08 bne- cr7,4000069c <send_c_ESCIA+0x2c>
40000698: 4b ff ff ec b 40000684 <send_c_ESCIA+0x14>
..\src\FESC_src\/FESC_5554_ESCI.c:27
ESCI_A.SR.R = 0x80000000;
4000069c: 3d 20 ff fb lis r9,-5
400006a0: 3c 00 80 00 lis r0,-32768
400006a4: 90 09 00 08 stw r0,8(r9)
..\src\FESC_src\/FESC_5554_ESCI.c:28
ESCI_A.DR.B.D = schar;
400006a8: 3d 20 ff fb lis r9,-5
400006ac: 88 1f 00 08 lbz r0,8(r31)
400006b0: 98 09 00 07 stb r0,7(r9)
..\src\FESC_src\/FESC_5554_ESCI.c:29
}
400006b4: 81 61 00 00 lwz r11,0(r1)
400006b8: 83 eb ff fc lwz r31,-4(r11)
400006bc: 7d 61 5b 78 mr r1,r11
400006c0: 4e 80 00 20 blr
400006c4 <get_c_ESCI_A>:
get_c_ESCI_A():
..\src\FESC_src\/FESC_5554_ESCI.c:32
uint8_t get_c_ESCI_A(void)
{ uint8_t RecData;
400006c4: 94 21 ff e0 stwu r1,-32(r1)
400006c8: 93 e1 00 1c stw r31,28(r1)
400006cc: 7c 3f 0b 78 mr r31,r1
..\src\FESC_src\/FESC_5554_ESCI.c:33
while(ESCI_A.SR.B.RDRF == 0 ) {}
400006d0: 3d 20 ff fb lis r9,-5
400006d4: 88 09 00 08 lbz r0,8(r9)
400006d8: 54 00 df fe rlwinm r0,r0,27,31,31
400006dc: 2f 80 00 00 cmpwi cr7,r0,0
400006e0: 40 9e 00 08 bne- cr7,400006e8 <get_c_ESCI_A+0x24>
400006e4: 4b ff ff ec b 400006d0 <get_c_ESCI_A+0xc>
..\src\FESC_src\/FESC_5554_ESCI.c:34
RecData = ESCI_A.DR.B.D;
400006e8: 3d 20 ff fb lis r9,-5
400006ec: 88 09 00 07 lbz r0,7(r9)
400006f0: 98 1f 00 08 stb r0,8(r31)
..\src\FESC_src\/FESC_5554_ESCI.c:35
ESCI_A.SR.R = 0x20000000;
400006f4: 3d 20 ff fb lis r9,-5
400006f8: 3c 00 20 00 lis r0,8192
400006fc: 90 09 00 08 stw r0,8(r9)
..\src\FESC_src\/FESC_5554_ESCI.c:36
return(RecData);
40000700: 88 1f 00 08 lbz r0,8(r31)
40000704: 54 00 06 3e clrlwi r0,r0,24
..\src\FESC_src\/FESC_5554_ESCI.c:37
}
40000708: 7c 03 03 78 mr r3,r0
4000070c: 81 61 00 00 lwz r11,0(r1)
40000710: 83 eb ff fc lwz r31,-4(r11)
40000714: 7d 61 5b 78 mr r1,r11
40000718: 4e 80 00 20 blr
4000071c <send_c_ESCIB>:
send_c_ESCIB():
..\src\FESC_src\/FESC_5554_ESCI.c:40
void send_c_ESCIB(uint8_t schar)
{
4000071c: 94 21 ff e0 stwu r1,-32(r1)
40000720: 93 e1 00 1c stw r31,28(r1)
40000724: 7c 3f 0b 78 mr r31,r1
40000728: 7c 60 1b 78 mr r0,r3
4000072c: 98 1f 00 08 stb r0,8(r31)
..\src\FESC_src\/FESC_5554_ESCI.c:41
while(ESCI_B.SR.B.TDRE == 1){}
40000730: 3d 20 ff fb lis r9,-5
40000734: 61 29 40 00 ori r9,r9,16384
40000738: 88 09 00 08 lbz r0,8(r9)
4000073c: 54 00 cf fe rlwinm r0,r0,25,31,31
40000740: 2f 80 00 01 cmpwi cr7,r0,1
40000744: 40 9e 00 08 bne- cr7,4000074c <send_c_ESCIB+0x30>
40000748: 4b ff ff e8 b 40000730 <send_c_ESCIB+0x14>
..\src\FESC_src\/FESC_5554_ESCI.c:42
ESCI_B.SR.R = 0x80000000;
4000074c: 3d 20 ff fb lis r9,-5
40000750: 61 29 40 00 ori r9,r9,16384
40000754: 3c 00 80 00 lis r0,-32768
40000758: 90 09 00 08 stw r0,8(r9)
..\src\FESC_src\/FESC_5554_ESCI.c:43
ESCI_B.DR.B.D = schar;
4000075c: 3d 20 ff fb lis r9,-5
40000760: 61 29 40 00 ori r9,r9,16384
40000764: 88 1f 00 08 lbz r0,8(r31)
40000768: 98 09 00 07 stb r0,7(r9)
..\src\FESC_src\/FESC_5554_ESCI.c:44
}
4000076c: 81 61 00 00 lwz r11,0(r1)
40000770: 83 eb ff fc lwz r31,-4(r11)
40000774: 7d 61 5b 78 mr r1,r11
40000778: 4e 80 00 20 blr
4000077c <get_c_ESCI_B>:
get_c_ESCI_B():
..\src\FESC_src\/FESC_5554_ESCI.c:47
uint8_t get_c_ESCI_B(void)
{ uint8_t RecData;
4000077c: 94 21 ff e0 stwu r1,-32(r1)
40000780: 93 e1 00 1c stw r31,28(r1)
40000784: 7c 3f 0b 78 mr r31,r1
..\src\FESC_src\/FESC_5554_ESCI.c:48
while(ESCI_B.SR.B.RDRF == 0 ) {}
40000788: 3d 20 ff fb lis r9,-5
4000078c: 61 29 40 00 ori r9,r9,16384
40000790: 88 09 00 08 lbz r0,8(r9)
40000794: 54 00 df fe rlwinm r0,r0,27,31,31
40000798: 2f 80 00 00 cmpwi cr7,r0,0
4000079c: 40 9e 00 08 bne- cr7,400007a4 <get_c_ESCI_B+0x28>
400007a0: 4b ff ff e8 b 40000788 <get_c_ESCI_B+0xc>
..\src\FESC_src\/FESC_5554_ESCI.c:49
RecData = ESCI_B.DR.B.D;
400007a4: 3d 20 ff fb lis r9,-5
400007a8: 61 29 40 00 ori r9,r9,16384
400007ac: 88 09 00 07 lbz r0,7(r9)
400007b0: 98 1f 00 08 stb r0,8(r31)
..\src\FESC_src\/FESC_5554_ESCI.c:50
ESCI_B.SR.R = 0x20000000;
400007b4: 3d 20 ff fb lis r9,-5
400007b8: 61 29 40 00 ori r9,r9,16384
400007bc: 3c 00 20 00 lis r0,8192
400007c0: 90 09 00 08 stw r0,8(r9)
..\src\FESC_src\/FESC_5554_ESCI.c:51
return(RecData);
400007c4: 88 1f 00 08 lbz r0,8(r31)
400007c8: 54 00 06 3e clrlwi r0,r0,24
..\src\FESC_src\/FESC_5554_ESCI.c:52
}
400007cc: 7c 03 03 78 mr r3,r0
400007d0: 81 61 00 00 lwz r11,0(r1)
400007d4: 83 eb ff fc lwz r31,-4(r11)
400007d8: 7d 61 5b 78 mr r1,r11
400007dc: 4e 80 00 20 blr
400007e0 <init_FPGA_SPI>:
init_FPGA_SPI():
..\src\FESC_src\/FESC_5554_FSPI.c:9
/* RETURN NOTES : None */
/* WARNING : None */
/*************************************************************************/
void init_FPGA_SPI(void)
{ uint8_t i;
400007e0: 94 21 ff e0 stwu r1,-32(r1)
400007e4: 93 e1 00 1c stw r31,28(r1)
400007e8: 7c 3f 0b 78 mr r31,r1
..\src\FESC_src\/FESC_5554_FSPI.c:10
for(i=0;i<8;i++)
400007ec: 38 00 00 00 li r0,0
400007f0: 98 1f 00 08 stb r0,8(r31)
400007f4: 88 1f 00 08 lbz r0,8(r31)
400007f8: 54 00 06 3e clrlwi r0,r0,24
400007fc: 2b 80 00 07 cmplwi cr7,r0,7
40000800: 41 9d 00 58 bgt- cr7,40000858 <init_FPGA_SPI+0x78>
..\src\FESC_src\/FESC_5554_FSPI.c:12
{
SXC.CH[i].SXC_CR.B.TCFC = 1;
40000804: 3d 20 3f c0 lis r9,16320
40000808: 88 1f 00 08 lbz r0,8(r31)
4000080c: 54 00 06 3e clrlwi r0,r0,24
40000810: 54 00 30 32 rlwinm r0,r0,6,0,25
40000814: 7d 20 4a 14 add r9,r0,r9
40000818: 88 09 00 03 lbz r0,3(r9)
4000081c: 64 00 ff ff oris r0,r0,65535
40000820: 60 00 ff 80 ori r0,r0,65408
40000824: 98 09 00 03 stb r0,3(r9)
..\src\FESC_src\/FESC_5554_FSPI.c:13
SXC.CH[i].SXC_CR.B.RDFC = 1;
40000828: 3d 20 3f c0 lis r9,16320
4000082c: 88 1f 00 08 lbz r0,8(r31)
40000830: 54 00 06 3e clrlwi r0,r0,24
40000834: 54 00 30 32 rlwinm r0,r0,6,0,25
40000838: 7d 20 4a 14 add r9,r0,r9
4000083c: 88 09 00 03 lbz r0,3(r9)
40000840: 60 00 00 40 ori r0,r0,64
40000844: 98 09 00 03 stb r0,3(r9)
..\src\FESC_src\/FESC_5554_FSPI.c:10
40000848: 89 3f 00 08 lbz r9,8(r31)
4000084c: 38 09 00 01 addi r0,r9,1
40000850: 98 1f 00 08 stb r0,8(r31)
40000854: 4b ff ff a0 b 400007f4 <init_FPGA_SPI+0x14>
..\src\FESC_src\/FESC_5554_FSPI.c:15
}
for(i=0;i<6;i++) SXC.CH[i].SPI_BAUD_REG.B.BAUD = 25; // 120MHz/(32*25) = 150Kbps
40000858: 38 00 00 00 li r0,0
4000085c: 98 1f 00 08 stb r0,8(r31)
40000860: 88 1f 00 08 lbz r0,8(r31)
40000864: 54 00 06 3e clrlwi r0,r0,24
40000868: 2b 80 00 05 cmplwi cr7,r0,5
4000086c: 41 9d 00 30 bgt- cr7,4000089c <init_FPGA_SPI+0xbc>
40000870: 3d 20 3f c0 lis r9,16320
40000874: 88 1f 00 08 lbz r0,8(r31)
40000878: 54 00 06 3e clrlwi r0,r0,24
4000087c: 54 00 30 32 rlwinm r0,r0,6,0,25
40000880: 7d 20 4a 14 add r9,r0,r9
40000884: 38 00 00 19 li r0,25
40000888: 98 09 00 0f stb r0,15(r9)
4000088c: 89 3f 00 08 lbz r9,8(r31)
40000890: 38 09 00 01 addi r0,r9,1
40000894: 98 1f 00 08 stb r0,8(r31)
40000898: 4b ff ff c8 b 40000860 <init_FPGA_SPI+0x80>
..\src\FESC_src\/FESC_5554_FSPI.c:16
SXC.CH[6].SPI_BAUD_REG.B.BAUD = 5; // 120MHz/(32*5) = 750Kbps
4000089c: 3d 20 3f c0 lis r9,16320
400008a0: 38 00 00 05 li r0,5
400008a4: 98 09 01 8f stb r0,399(r9)
..\src\FESC_src\/FESC_5554_FSPI.c:17
SXC.CH[7].SPI_BAUD_REG.B.BAUD = 5;
400008a8: 3d 20 3f c0 lis r9,16320
400008ac: 38 00 00 05 li r0,5
400008b0: 98 09 01 cf stb r0,463(r9)
..\src\FESC_src\/FESC_5554_FSPI.c:18
}
400008b4: 81 61 00 00 lwz r11,0(r1)
400008b8: 83 eb ff fc lwz r31,-4(r11)
400008bc: 7d 61 5b 78 mr r1,r11
400008c0: 4e 80 00 20 blr
400008c4 <FPGA_SPI_ready_send>:
FPGA_SPI_ready_send():
..\src\FESC_src\/FESC_5554_FSPI.c:21
uint8_t FPGA_SPI_ready_send(uint8_t ch)
{
400008c4: 94 21 ff e0 stwu r1,-32(r1)
400008c8: 93 e1 00 1c stw r31,28(r1)
400008cc: 7c 3f 0b 78 mr r31,r1
400008d0: 7c 60 1b 78 mr r0,r3
400008d4: 98 1f 00 08 stb r0,8(r31)
..\src\FESC_src\/FESC_5554_FSPI.c:22
if(SXC.CH[ch].SXC_SR.B.BUSY==0) return(1);
400008d8: 3d 20 3f c0 lis r9,16320
400008dc: 88 1f 00 08 lbz r0,8(r31)
400008e0: 54 00 06 3e clrlwi r0,r0,24
400008e4: 54 00 30 32 rlwinm r0,r0,6,0,25
400008e8: 7d 20 4a 14 add r9,r0,r9
400008ec: 88 09 00 07 lbz r0,7(r9)
400008f0: 54 00 df fe rlwinm r0,r0,27,31,31
400008f4: 2f 80 00 00 cmpwi cr7,r0,0
400008f8: 40 9e 00 10 bne- cr7,40000908 <FPGA_SPI_ready_send+0x44>
400008fc: 38 00 00 01 li r0,1
40000900: 90 1f 00 0c stw r0,12(r31)
40000904: 48 00 00 0c b 40000910 <FPGA_SPI_ready_send+0x4c>
..\src\FESC_src\/FESC_5554_FSPI.c:23
else return(0);
40000908: 38 00 00 00 li r0,0
4000090c: 90 1f 00 0c stw r0,12(r31)
..\src\FESC_src\/FESC_5554_FSPI.c:24
}
40000910: 80 7f 00 0c lwz r3,12(r31)
40000914: 81 61 00 00 lwz r11,0(r1)
40000918: 83 eb ff fc lwz r31,-4(r11)
4000091c: 7d 61 5b 78 mr r1,r11
40000920: 4e 80 00 20 blr
40000924 <FPGA_SPI_ready_read>:
FPGA_SPI_ready_read():
..\src\FESC_src\/FESC_5554_FSPI.c:26
uint8_t FPGA_SPI_ready_read(uint8_t ch)
{
40000924: 94 21 ff e0 stwu r1,-32(r1)
40000928: 93 e1 00 1c stw r31,28(r1)
4000092c: 7c 3f 0b 78 mr r31,r1
40000930: 7c 60 1b 78 mr r0,r3
40000934: 98 1f 00 08 stb r0,8(r31)
..\src\FESC_src\/FESC_5554_FSPI.c:27
if(SXC.CH[ch].SXC_SR.B.RDF==1) return(1);
40000938: 3d 20 3f c0 lis r9,16320
4000093c: 88 1f 00 08 lbz r0,8(r31)
40000940: 54 00 06 3e clrlwi r0,r0,24
40000944: 54 00 30 32 rlwinm r0,r0,6,0,25
40000948: 7d 20 4a 14 add r9,r0,r9
4000094c: 88 09 00 07 lbz r0,7(r9)
40000950: 54 00 d7 fe rlwinm r0,r0,26,31,31
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