📄 ram.dis
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.\ram.elf: file format elf32-powerpc
Disassembly of section .text:
40000000 <pad_func_config>:
pad_func_config():
..\src\FESC_src\/FESC_5554_general.c:2
void pad_func_config( uint16_t port, uint16_t config)
{
40000000: 94 21 ff e0 stwu r1,-32(r1)
40000004: 93 e1 00 1c stw r31,28(r1)
40000008: 7c 3f 0b 78 mr r31,r1
4000000c: 7c 60 1b 78 mr r0,r3
40000010: 7c 89 23 78 mr r9,r4
40000014: b0 1f 00 08 sth r0,8(r31)
40000018: 7d 20 4b 78 mr r0,r9
4000001c: b0 1f 00 0a sth r0,10(r31)
..\src\FESC_src\/FESC_5554_general.c:3
SIU.PCR[port].R = config;
40000020: 3d 20 c3 f9 lis r9,-15367
40000024: a0 1f 00 08 lhz r0,8(r31)
40000028: 54 00 04 3e clrlwi r0,r0,16
4000002c: 54 00 08 3c rlwinm r0,r0,1,0,30
40000030: 7d 20 4a 14 add r9,r0,r9
40000034: 39 29 00 40 addi r9,r9,64
40000038: a0 1f 00 0a lhz r0,10(r31)
4000003c: b0 09 00 00 sth r0,0(r9)
..\src\FESC_src\/FESC_5554_general.c:4
}
40000040: 81 61 00 00 lwz r11,0(r1)
40000044: 83 eb ff fc lwz r31,-4(r11)
40000048: 7d 61 5b 78 mr r1,r11
4000004c: 4e 80 00 20 blr
40000050 <set_GPIO>:
set_GPIO():
..\src\FESC_src\/FESC_5554_general.c:10
/*================================================*/
/* GPIO */
/*================================================*/
void set_GPIO(uint8_t pin,uint8_t val)
{
40000050: 94 21 ff e0 stwu r1,-32(r1)
40000054: 93 e1 00 1c stw r31,28(r1)
40000058: 7c 3f 0b 78 mr r31,r1
4000005c: 7c 60 1b 78 mr r0,r3
40000060: 7c 89 23 78 mr r9,r4
40000064: 98 1f 00 08 stb r0,8(r31)
40000068: 7d 20 4b 78 mr r0,r9
4000006c: 98 1f 00 09 stb r0,9(r31)
..\src\FESC_src\/FESC_5554_general.c:11
if( val > 1) //toggle PIN
40000070: 88 1f 00 09 lbz r0,9(r31)
40000074: 54 00 06 3e clrlwi r0,r0,24
40000078: 2b 80 00 01 cmplwi cr7,r0,1
4000007c: 40 9d 00 40 ble- cr7,400000bc <set_GPIO+0x6c>
..\src\FESC_src\/FESC_5554_general.c:12
SIU.GPDO[pin].R = !SIU.GPDO[pin].R; /* Invert gpio port */
40000080: 3d 20 c3 f9 lis r9,-15367
40000084: 88 1f 00 08 lbz r0,8(r31)
40000088: 54 00 06 3e clrlwi r0,r0,24
4000008c: 7d 69 02 14 add r11,r9,r0
40000090: 3d 20 c3 f9 lis r9,-15367
40000094: 88 1f 00 08 lbz r0,8(r31)
40000098: 54 00 06 3e clrlwi r0,r0,24
4000009c: 7d 29 02 14 add r9,r9,r0
400000a0: 88 09 06 00 lbz r0,1536(r9)
400000a4: 54 00 06 3e clrlwi r0,r0,24
400000a8: 2f 80 00 00 cmpwi cr7,r0,0
400000ac: 7c 00 00 26 mfcr r0
400000b0: 54 00 ff fe rlwinm r0,r0,31,31,31
400000b4: 98 0b 06 00 stb r0,1536(r11)
400000b8: 48 00 00 1c b 400000d4 <set_GPIO+0x84>
..\src\FESC_src\/FESC_5554_general.c:14
else
SIU.GPDO[pin].R = val;
400000bc: 3d 20 c3 f9 lis r9,-15367
400000c0: 88 1f 00 08 lbz r0,8(r31)
400000c4: 54 00 06 3e clrlwi r0,r0,24
400000c8: 7d 29 02 14 add r9,r9,r0
400000cc: 88 1f 00 09 lbz r0,9(r31)
400000d0: 98 09 06 00 stb r0,1536(r9)
..\src\FESC_src\/FESC_5554_general.c:15
}
400000d4: 81 61 00 00 lwz r11,0(r1)
400000d8: 83 eb ff fc lwz r31,-4(r11)
400000dc: 7d 61 5b 78 mr r1,r11
400000e0: 4e 80 00 20 blr
400000e4 <set_led>:
set_led():
..\src\FESC_src\/FESC_5554_general.c:18
/*================================================*/
void set_led(uint8_t led, uint8_t status)
{
400000e4: 94 21 ff e0 stwu r1,-32(r1)
400000e8: 7c 08 02 a6 mflr r0
400000ec: 93 e1 00 1c stw r31,28(r1)
400000f0: 90 01 00 24 stw r0,36(r1)
400000f4: 7c 3f 0b 78 mr r31,r1
400000f8: 7c 60 1b 78 mr r0,r3
400000fc: 7c 89 23 78 mr r9,r4
40000100: 98 1f 00 08 stb r0,8(r31)
40000104: 7d 20 4b 78 mr r0,r9
40000108: 98 1f 00 09 stb r0,9(r31)
..\src\FESC_src\/FESC_5554_general.c:19
set_GPIO(led,status);
4000010c: 88 1f 00 08 lbz r0,8(r31)
40000110: 54 09 06 3e clrlwi r9,r0,24
40000114: 88 1f 00 09 lbz r0,9(r31)
40000118: 54 00 06 3e clrlwi r0,r0,24
4000011c: 7d 23 4b 78 mr r3,r9
40000120: 7c 04 03 78 mr r4,r0
40000124: 4b ff ff 2d bl 40000050 <set_GPIO>
..\src\FESC_src\/FESC_5554_general.c:20
}
40000128: 81 61 00 00 lwz r11,0(r1)
4000012c: 80 0b 00 04 lwz r0,4(r11)
40000130: 7c 08 03 a6 mtlr r0
40000134: 83 eb ff fc lwz r31,-4(r11)
40000138: 7d 61 5b 78 mr r1,r11
4000013c: 4e 80 00 20 blr
40000140 <delay>:
delay():
..\src\FESC_src\/FESC_5554_general.c:30
/*************************************************************************/
/* FUNCTION : delay */
/* PURPOSE : */
/* INPUT NOTES : */
/* RETURN NOTES : None */
/* WARNING : None */
/*************************************************************************/
void delay(uint32_t cnt)
{
40000140: 94 21 ff e0 stwu r1,-32(r1)
40000144: 93 e1 00 1c stw r31,28(r1)
40000148: 7c 3f 0b 78 mr r31,r1
4000014c: 90 7f 00 08 stw r3,8(r31)
..\src\FESC_src\/FESC_5554_general.c:31
uint32_t i=0;
40000150: 38 00 00 00 li r0,0
40000154: 90 1f 00 0c stw r0,12(r31)
..\src\FESC_src\/FESC_5554_general.c:32
while(i<cnt) i++;
40000158: 80 1f 00 0c lwz r0,12(r31)
4000015c: 81 3f 00 08 lwz r9,8(r31)
40000160: 7f 80 48 40 cmplw cr7,r0,r9
40000164: 40 9c 00 14 bge- cr7,40000178 <delay+0x38>
40000168: 81 3f 00 0c lwz r9,12(r31)
4000016c: 38 09 00 01 addi r0,r9,1
40000170: 90 1f 00 0c stw r0,12(r31)
40000174: 4b ff ff e4 b 40000158 <delay+0x18>
..\src\FESC_src\/FESC_5554_general.c:33
}
40000178: 81 61 00 00 lwz r11,0(r1)
4000017c: 83 eb ff fc lwz r31,-4(r11)
40000180: 7d 61 5b 78 mr r1,r11
40000184: 4e 80 00 20 blr
40000188 <char2num>:
char2num():
..\src\FESC_src\/FESC_5554_general.c:43
/*************************************************************************/
/* FUNCTION : char2num */
/* PURPOSE : conv a character to number */
/* INPUT NOTES : */
/* RETURN NOTES : None */
/* WARNING : for char not in ‘0123456789abcdefABCDEF', return0 */
/*************************************************************************/
uint8_t char2num(uint8_t inch)
{
40000188: 94 21 ff e0 stwu r1,-32(r1)
4000018c: 93 e1 00 1c stw r31,28(r1)
40000190: 7c 3f 0b 78 mr r31,r1
40000194: 7c 60 1b 78 mr r0,r3
40000198: 98 1f 00 08 stb r0,8(r31)
..\src\FESC_src\/FESC_5554_general.c:45
uint8_t ch;
ch = toupper(inch);
4000019c: 88 1f 00 08 lbz r0,8(r31)
400001a0: 54 00 06 3e clrlwi r0,r0,24
400001a4: 90 1f 00 0c stw r0,12(r31)
400001a8: 81 3f 00 0c lwz r9,12(r31)
400001ac: 91 3f 00 14 stw r9,20(r31)
400001b0: 81 7f 00 0c lwz r11,12(r31)
400001b4: 3d 20 40 01 lis r9,16385
400001b8: 38 09 84 d1 addi r0,r9,-31535
400001bc: 7d 2b 02 14 add r9,r11,r0
400001c0: 88 09 00 00 lbz r0,0(r9)
400001c4: 54 00 06 3e clrlwi r0,r0,24
400001c8: 54 00 07 bc rlwinm r0,r0,0,30,30
400001cc: 2f 80 00 00 cmpwi cr7,r0,0
400001d0: 41 9e 00 10 beq- cr7,400001e0 <char2num+0x58>
400001d4: 81 3f 00 14 lwz r9,20(r31)
400001d8: 39 29 ff e0 addi r9,r9,-32
400001dc: 91 3f 00 14 stw r9,20(r31)
400001e0: 81 3f 00 14 lwz r9,20(r31)
400001e4: 7d 20 4b 78 mr r0,r9
400001e8: 98 1f 00 09 stb r0,9(r31)
..\src\FESC_src\/FESC_5554_general.c:46
if (( ch <= '9') && (ch >= '0')) return(ch-'0');
400001ec: 88 1f 00 09 lbz r0,9(r31)
400001f0: 54 00 06 3e clrlwi r0,r0,24
400001f4: 2b 80 00 39 cmplwi cr7,r0,57
400001f8: 41 9d 00 28 bgt- cr7,40000220 <char2num+0x98>
400001fc: 88 1f 00 09 lbz r0,9(r31)
40000200: 54 00 06 3e clrlwi r0,r0,24
40000204: 2b 80 00 2f cmplwi cr7,r0,47
40000208: 40 9d 00 18 ble- cr7,40000220 <char2num+0x98>
4000020c: 89 3f 00 09 lbz r9,9(r31)
40000210: 38 09 ff d0 addi r0,r9,-48
40000214: 54 00 06 3e clrlwi r0,r0,24
40000218: 90 1f 00 10 stw r0,16(r31)
4000021c: 48 00 00 40 b 4000025c <char2num+0xd4>
..\src\FESC_src\/FESC_5554_general.c:47
else if (( ch <= 'F') && (ch >= 'A')) return(ch-'A'+10);
40000220: 88 1f 00 09 lbz r0,9(r31)
40000224: 54 00 06 3e clrlwi r0,r0,24
40000228: 2b 80 00 46 cmplwi cr7,r0,70
4000022c: 41 9d 00 28 bgt- cr7,40000254 <char2num+0xcc>
40000230: 88 1f 00 09 lbz r0,9(r31)
40000234: 54 00 06 3e clrlwi r0,r0,24
40000238: 2b 80 00 40 cmplwi cr7,r0,64
4000023c: 40 9d 00 18 ble- cr7,40000254 <char2num+0xcc>
40000240: 89 3f 00 09 lbz r9,9(r31)
40000244: 38 09 ff c9 addi r0,r9,-55
40000248: 54 00 06 3e clrlwi r0,r0,24
4000024c: 90 1f 00 10 stw r0,16(r31)
40000250: 48 00 00 0c b 4000025c <char2num+0xd4>
..\src\FESC_src\/FESC_5554_general.c:48
else return(0);
40000254: 38 00 00 00 li r0,0
40000258: 90 1f 00 10 stw r0,16(r31)
..\src\FESC_src\/FESC_5554_general.c:49
}
4000025c: 80 7f 00 10 lwz r3,16(r31)
40000260: 81 61 00 00 lwz r11,0(r1)
40000264: 83 eb ff fc lwz r31,-4(r11)
40000268: 7d 61 5b 78 mr r1,r11
4000026c: 4e 80 00 20 blr
40000270 <init_dpb>:
init_dpb():
..\src\FESC_src\/FESC_5554_general.c:67
/*-----------------------------------------------*/
/* Dual-Port buffer */
/* one routine pushs data into DPB */
/* another routine pops data from it and process */
/* it loSBP_RTSTUS_OKs like a FIFO, dual-port access */
/*-----------------------------------------------*/
/*************************************************************************/
/* FUNCTION : Flush_DP_Buf */
/* PURPOSE : */
/* INPUT NOTES : */
/* RETURN NOTES : None */
/* WARNING : None */
/*************************************************************************/
void init_dpb(DP_BUF_tag* pt,uint8_t* mem,uint32_t len)
{ uint32_t i;
40000270: 94 21 ff e0 stwu r1,-32(r1)
40000274: 93 e1 00 1c stw r31,28(r1)
40000278: 7c 3f 0b 78 mr r31,r1
4000027c: 90 7f 00 08 stw r3,8(r31)
40000280: 90 9f 00 0c stw r4,12(r31)
40000284: 90 bf 00 10 stw r5,16(r31)
..\src\FESC_src\/FESC_5554_general.c:68
pt->n = 0;
40000288: 81 3f 00 08 lwz r9,8(r31)
4000028c: 38 00 00 00 li r0,0
40000290: 90 09 00 00 stw r0,0(r9)
..\src\FESC_src\/FESC_5554_general.c:69
pt->in_n = 0;
40000294: 81 3f 00 08 lwz r9,8(r31)
40000298: 38 00 00 00 li r0,0
4000029c: 90 09 00 04 stw r0,4(r9)
..\src\FESC_src\/FESC_5554_general.c:70
pt->out_n= 0;
400002a0: 81 3f 00 08 lwz r9,8(r31)
400002a4: 38 00 00 00 li r0,0
400002a8: 90 09 00 08 stw r0,8(r9)
..\src\FESC_src\/FESC_5554_general.c:71
pt->len = len;
400002ac: 81 3f 00 08 lwz r9,8(r31)
400002b0: 80 1f 00 10 lwz r0,16(r31)
400002b4: 90 09 00 0c stw r0,12(r9)
..\src\FESC_src\/FESC_5554_general.c:72
pt->addr = mem;
400002b8: 81 3f 00 08 lwz r9,8(r31)
400002bc: 80 1f 00 0c lwz r0,12(r31)
400002c0: 90 09 00 10 stw r0,16(r9)
..\src\FESC_src\/FESC_5554_general.c:73
for(i=0;i<len;i++) *(mem+i) = 0;
400002c4: 38 00 00 00 li r0,0
400002c8: 90 1f 00 14 stw r0,20(r31)
400002cc: 80 1f 00 14 lwz r0,20(r31)
400002d0: 81 3f 00 10 lwz r9,16(r31)
400002d4: 7f 80 48 40 cmplw cr7,r0,r9
400002d8: 40 9c 00 28 bge- cr7,40000300 <init_dpb+0x90>
400002dc: 81 3f 00 14 lwz r9,20(r31)
400002e0: 80 1f 00 0c lwz r0,12(r31)
400002e4: 7d 29 02 14 add r9,r9,r0
400002e8: 38 00 00 00 li r0,0
400002ec: 98 09 00 00 stb r0,0(r9)
400002f0: 81 3f 00 14 lwz r9,20(r31)
400002f4: 38 09 00 01 addi r0,r9,1
400002f8: 90 1f 00 14 stw r0,20(r31)
400002fc: 4b ff ff d0 b 400002cc <init_dpb+0x5c>
..\src\FESC_src\/FESC_5554_general.c:74
}
40000300: 81 61 00 00 lwz r11,0(r1)
40000304: 83 eb ff fc lwz r31,-4(r11)
40000308: 7d 61 5b 78 mr r1,r11
4000030c: 4e 80 00 20 blr
40000310 <push_dpb_data>:
push_dpb_data():
..\src\FESC_src\/FESC_5554_general.c:83
/*************************************************************************/
/* FUNCTION : push 1 data into ring buf */
/* PURPOSE : */
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