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📄 dctaan_xmm.asm

📁 Intel AN&N FAST dct MMX and X
💻 ASM
📖 第 1 页 / 共 2 页
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pshufw mm1,mm4,0ech     ; [ecx+16] to avoid MOB stall  (7,1)->1
pinsrw mm1,[ecx+7*2-8],0		   ; (7,0)->0	; moved up
movq  mmword ptr [ecx+16*3],mm5   ; out3: v47-v34 
;pinsrw mm1,[ecx+16+7*2-8],1		   ; (7,1)->1 ; moved 
;insrw mm1,[ecx+16*3+7*2-8],3		   ; (7,1)->3	; moved up
; this 3 instructions are replacement for the pinsert to avoid MOB stall
pand   mm5,msword ; keep only m.s. word (3)
pinsrw mm0,[ecx+16*2-8],2		   ; (0,2)->2  ; moved up
pand   mm1,notmsword ;	keep all except m.s. word
pinsrw mm0,[ecx+16*3-8],3		   ; (0,3)->3	; moved up
por    mm1,mm5

sub  ecx,8  ; point back to the first 4 columns/rows. 

; first 4 rows 
;movq mm0, mmword ptr [ecx]	   ; v0	; moved up
;pinsrw mm0,[ecx+16],1		   ; (0,1)->1  ; moved up
;pinsrw mm0,[ecx+16*2],2		   ; (0,2)->2  ; moved up
;pinsrw mm0,[ecx+16*3],3		   ; (0,3)->3	; moved up
;movq mm1, mmword ptr [ecx+16*7]	   ; v7
;pinsrw mm1,[ecx+7*2],0		   ; (7,0)->0	; moved up
;pinsrw mm1,[ecx+16+7*2],1		   ; (7,1)->1 ; moved up
pinsrw mm1,[ecx+16*2+7*2],2		   ; (7,1)->2
;pinsrw mm1,[ecx+16*3+7*2],3		   ; (7,1)->3
movq  mm2,mm0                  ; duplicate v0 
paddw mm0,mm1                  ; v00: v0+v7  
psubw mm2,mm1                  ; v07: v0-v7  

;movq mm1, mmword ptr [ecx+16]	   ; v1
pinsrw mm1,[ecx+1*2],0		   ; (7,0)->0
pinsrw mm1,[ecx+16+1*2],1		   ; (7,1)->1
pinsrw mm1,[ecx+16*2+1*2],2		   ; (7,1)->2
pinsrw mm1,[ecx+16*3+1*2],3		   ; (7,1)->3	; moved up
;movq mm3, mmword ptr [ecx+16*6]	   ; v6
pinsrw mm3,[ecx+6*2],0		   ; (7,0)->0
pinsrw mm3,[ecx+16+6*2],1		   ; (7,1)->1
pinsrw mm3,[ecx+16*2+6*2],2		   ; (7,1)->2
pinsrw mm3,[ecx+16*3+6*2],3		   ; (7,1)->3
movq  mm4,mm1                  ; duplicate v1 
paddw mm1,mm3                  ; v01: v1+v6  
psubw mm4,mm3                  ; v06: v1-v6  

;movq mm3, mmword ptr [ecx+16*2] ; v2
pinsrw mm3,[ecx+2*2],0		   ; (7,0)->0
pinsrw mm3,[ecx+16+2*2],1		   ; (7,1)->1
pinsrw mm3,[ecx+16*2+2*2],2		   ; (7,1)->2
pinsrw mm3,[ecx+16*3+2*2],3		   ; (7,1)->3
;movq mm5, mmword ptr [ecx+16*5]	   ; v5
pinsrw mm5,[ecx+5*2],0		   ; (7,0)->0
pinsrw mm5,[ecx+16+5*2],1		   ; (7,1)->1
pinsrw mm5,[ecx+16*2+5*2],2		   ; (7,1)->2
pinsrw mm5,[ecx+16*3+5*2],3		   ; (7,1)->3
movq  mm6,mm3                  ; duplicate v2 
paddw mm3,mm5                  ; v02: v2+v5  
psubw mm6,mm5                  ; v05: v2-v5  

;movq mm5, mmword ptr [ecx+16*3]	   ; v3
pinsrw mm5,[ecx+3*2],0		   ; (7,0)->0
pinsrw mm5,[ecx+16+3*2],1		   ; (7,1)->1
pinsrw mm5,[ecx+16*2+3*2],2		   ; (7,1)->2
pinsrw mm5,[ecx+16*3+3*2],3		   ; (7,1)->3
;movq mm7, mmword ptr [ecx+16*4]	   ; v4
pinsrw mm7,[ecx+4*2],0		   ; (7,0)->0
pinsrw mm7,[ecx+16+4*2],1		   ; (7,1)->1
pinsrw mm7,[ecx+16*2+4*2],2		   ; (7,1)->2
pinsrw mm7,[ecx+16*3+4*2],3		   ; (7,1)->3
movq  mmword ptr scratch1,mm7		; scratch1: v4   ; 
movq  mm7,mm5                  ; duplicate v3 
paddw mm5,scratch1             ; v03: v3+v4  
psubw mm7,scratch1             ; v04: v3-v4  
movq  mmword ptr scratch2,mm5 ; scratch2: v03
movq  mm5,mm0                  ; mm5: v00

movq  mmword ptr scratch3,mm3  ; scratc3: v02
movq  mm3,mm1                  ; duplicate v01

paddw mm1,scratch3             ; v11: v01+v02
psubw mm3,scratch3             ; v12: v01-v02
 
movq  mmword ptr scratch4,mm6  ; scratc4: v05
paddw mm0,scratch2             ; v10: v00+v03   
psubw mm5,scratch2             ; v13: v00-v03   
movq  mm6,mm0                  ; duplicate v10

paddw mm0,mm1          ; v10+v11
psubw mm6,mm1          ; v10-v11
 
movq  mmword ptr [edx],mm0   ; out0: v10+v11 
movq  mmword ptr [edx+16*4],mm6   ; out4: v10-v11 

movq  mm0,mm4                ; mm0: v06
paddw mm4,scratch4           ; v15: v05+v06 
paddw  mm0,mm2 		  		; v16: v07+v06


pmulhw mm4,mmword ptr WA3    ; v35': WA3*v15
psllw  mm4,16-NSHIFT         ; v35: compensate the coeefient scale

movq   mm6,mm4               ; duplicate v35
paddw  mm4,mm2               ; v45: v07+v35
psubw  mm2,mm6               ; v47: v07-v35
 
paddw  mm3,mm5               ; v22: v12+v13

pmulhw mm3,mmword ptr WA1    ; v32': WA3*v15
psllw  mm3,16-NSHIFT         ; v32: compensate the coeefient scale
movq   mm6,mm5               ; duplicate v13

paddw  mm5,mm3               ; v13+v32
psubw  mm6,mm3               ; v13-v32

movq  mmword ptr [edx+16*2],mm5   ; out2: v13+v32 
movq  mmword ptr [edx+16*6],mm6   ; out6: v13-v32 

paddw  mm7,scratch4			; v14n: v04+v05
movq   mm5,mm0              ; duplicate v16

psubw  mm0,mm7				; va1: v16-v14n
pmulhw mm5,mmword ptr WA4 		; v36'': v16*WA4
pmulhw mm7,mmword ptr WA2		; v34'': v14n*WA2
pmulhw mm0,mmword ptr WA5		; va0':  va1*WA5

psllw  mm5,16-WA4_SHIFT      ; v36: compensate the coeefient scale. Note that WA$ is scaled one bit less
psllw  mm7,16-NSHIFT         ; v34: compensate the coeefient scale
;psllw  mm0,16-WA5_SHIFT

psubw  mm5,mm0      ; v36': v36''-va0'
psubw  mm7,mm0      ; v34': v34''-va0'

movq   mm0,mm4       ; duplicate v45
paddw  mm4,mm5       ; v45+v36
psubw  mm0,mm5       ; v45-v36

movq  mmword ptr [edx+16*1],mm4   ; out1: v45+v36 
movq  mmword ptr [edx+16*7],mm0   ; out7: v45-v36 

movq   mm5,mm2       ; duplicate v47
paddw  mm2,mm7       ; v47+v34
psubw  mm5,mm7       ; v47-v34

movq  mmword ptr [edx+16*5],mm2   ; out5: v47+v34 
movq  mmword ptr [edx+16*3],mm5   ; out3: v47-v34 


; second 4 rows 
add  ecx,16*4  ; source - point to the second 4 rows. 
add  edx,8     ; destination - point to the second 4 columns (transposed)

movq mm0, mmword ptr [ecx]	   ; v0
pinsrw mm0,[ecx+16],1		   ; (0,1)->1
pinsrw mm0,[ecx+16*2],2		   ; (0,2)->2
pinsrw mm0,[ecx+16*3],3		   ; (0,3)->3
;movq mm1, mmword ptr [ecx+16*7]	   ; v7
pinsrw mm1,[ecx+7*2],0		   ; (7,0)->0
pinsrw mm1,[ecx+16+7*2],1		   ; (7,1)->1
pinsrw mm1,[ecx+16*2+7*2],2		   ; (7,1)->2
pinsrw mm1,[ecx+16*3+7*2],3		   ; (7,1)->3
movq  mm2,mm0                  ; duplicate v0 
paddw mm0,mm1                  ; v00: v0+v7  
psubw mm2,mm1                  ; v07: v0-v7  

;movq mm1, mmword ptr [ecx+16]	   ; v1
pinsrw mm1,[ecx+1*2],0		   ; (7,0)->0
pinsrw mm1,[ecx+16+1*2],1		   ; (7,1)->1
pinsrw mm1,[ecx+16*2+1*2],2		   ; (7,1)->2
pinsrw mm1,[ecx+16*3+1*2],3		   ; (7,1)->3
;movq mm3, mmword ptr [ecx+16*6]	   ; v6
pinsrw mm3,[ecx+6*2],0		   ; (7,0)->0
pinsrw mm3,[ecx+16+6*2],1		   ; (7,1)->1
pinsrw mm3,[ecx+16*2+6*2],2		   ; (7,1)->2
pinsrw mm3,[ecx+16*3+6*2],3		   ; (7,1)->3
movq  mm4,mm1                  ; duplicate v1 
paddw mm1,mm3                  ; v01: v1+v6  
psubw mm4,mm3                  ; v06: v1-v6  

;movq mm3, mmword ptr [ecx+16*2] ; v2
pinsrw mm3,[ecx+2*2],0		   ; (7,0)->0
pinsrw mm3,[ecx+16+2*2],1		   ; (7,1)->1
pinsrw mm3,[ecx+16*2+2*2],2		   ; (7,1)->2
pinsrw mm3,[ecx+16*3+2*2],3		   ; (7,1)->3
;movq mm5, mmword ptr [ecx+16*5]	   ; v5
pinsrw mm5,[ecx+5*2],0		   ; (7,0)->0
pinsrw mm5,[ecx+16+5*2],1		   ; (7,1)->1
pinsrw mm5,[ecx+16*2+5*2],2		   ; (7,1)->2
pinsrw mm5,[ecx+16*3+5*2],3		   ; (7,1)->3
movq  mm6,mm3                  ; duplicate v2 
paddw mm3,mm5                  ; v02: v2+v5  
psubw mm6,mm5                  ; v05: v2-v5  

;movq mm5, mmword ptr [ecx+16*3]	   ; v3
pinsrw mm5,[ecx+3*2],0		   ; (7,0)->0
pinsrw mm5,[ecx+16+3*2],1		   ; (7,1)->1
pinsrw mm5,[ecx+16*2+3*2],2		   ; (7,1)->2
pinsrw mm5,[ecx+16*3+3*2],3		   ; (7,1)->3
;movq mm7, mmword ptr [ecx+16*4]	   ; v4
pinsrw mm7,[ecx+4*2],0		   ; (7,0)->0
pinsrw mm7,[ecx+16+4*2],1		   ; (7,1)->1
pinsrw mm7,[ecx+16*2+4*2],2		   ; (7,1)->2
pinsrw mm7,[ecx+16*3+4*2],3		   ; (7,1)->3
movq  mmword ptr scratch1,mm7		; scratch1: v4   ; 
movq  mm7,mm5                  ; duplicate v3 
paddw mm5,scratch1             ; v03: v3+v4  
psubw mm7,scratch1             ; v04: v3-v4  
movq  mmword ptr scratch2,mm5 ; scratch2: v03
movq  mm5,mm0                  ; mm5: v00

movq  mmword ptr scratch3,mm3  ; scratc3: v02
movq  mm3,mm1                  ; duplicate v01

paddw mm1,scratch3             ; v11: v01+v02
psubw mm3,scratch3             ; v12: v01-v02
 
movq  mmword ptr scratch4,mm6  ; scratc4: v05
paddw mm0,scratch2             ; v10: v00+v03   
psubw mm5,scratch2             ; v13: v00-v03   
movq  mm6,mm0                  ; duplicate v10

paddw mm0,mm1          ; v10+v11
psubw mm6,mm1          ; v10-v11
 
movq  mmword ptr [edx],mm0   ; out0: v10+v11 
movq  mmword ptr [edx+16*4],mm6   ; out4: v10-v11 

movq  mm0,mm4                ; mm0: v06
paddw mm4,scratch4           ; v15: v05+v06 
paddw  mm0,mm2 		  		; v16: v07+v06


pmulhw mm4,mmword ptr WA3    ; v35': WA3*v15
psllw  mm4,16-NSHIFT         ; v35: compensate the coeefient scale

movq   mm6,mm4               ; duplicate v35
paddw  mm4,mm2               ; v45: v07+v35
psubw  mm2,mm6               ; v47: v07-v35
 
paddw  mm3,mm5               ; v22: v12+v13

pmulhw mm3,mmword ptr WA1    ; v32': WA3*v15
psllw  mm3,16-NSHIFT         ; v32: compensate the coeefient scale
movq   mm6,mm5               ; duplicate v13

paddw  mm5,mm3               ; v13+v32
psubw  mm6,mm3               ; v13-v32

movq  mmword ptr [edx+16*2],mm5   ; out2: v13+v32 
movq  mmword ptr [edx+16*6],mm6   ; out6: v13-v32 

paddw  mm7,scratch4			; v14n: v04+v05
movq   mm5,mm0              ; duplicate v16

psubw  mm0,mm7				; va1: v16-v14n
pmulhw mm5,mmword ptr WA4 		; v36'': v16*WA4
pmulhw mm7,mmword ptr WA2		; v34'': v14n*WA2
pmulhw mm0,mmword ptr WA5		; va0':  va1*WA5

psllw  mm5,16-WA4_SHIFT    ; v36: compensate the coeefient scale. Note that WA$ is scaled one bit less
psllw  mm7,16-NSHIFT         ; v34: compensate the coeefient scale
;psllw  mm0,16-WA5_SHIFT

psubw  mm5,mm0      ; v36': v36''-va0'
psubw  mm7,mm0      ; v34': v34''-va0'

movq   mm0,mm4       ; duplicate v45
paddw  mm4,mm5       ; v45+v36
psubw  mm0,mm5       ; v45-v36

movq  mmword ptr [edx+16*1],mm4   ; out1: v45+v36 
movq  mmword ptr [edx+16*7],mm0   ; out7: v45-v36 

movq   mm5,mm2       ; duplicate v47
paddw  mm2,mm7       ; v47+v34
psubw  mm5,mm7       ; v47-v34

movq  mmword ptr [edx+16*5],mm2   ; out5: v47+v34 
movq  mmword ptr [edx+16*3],mm5   ; out3: v47-v34 

;emms


ret	0


_dct8x8aan_xmm ENDP
_TEXT ENDS

END

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