📄 mytest.rpt
字号:
- - 8 B -- MEM_SGMT 0 8 0 1 |phaserom1:20|lpm_rom:lpm_rom_component|altrom:srom|segment0_5
- - 8 A -- MEM_SGMT 0 8 0 1 |phaserom1:20|lpm_rom:lpm_rom_component|altrom:srom|segment0_6
- - 6 C -- MEM_SGMT 0 8 0 1 |phaserom1:20|lpm_rom:lpm_rom_component|altrom:srom|segment0_7
- - 8 C -- MEM_SGMT 0 8 0 1 |phaserom2:34|lpm_rom:lpm_rom_component|altrom:srom|segment0_0
- - 3 C -- MEM_SGMT 0 8 0 1 |phaserom2:34|lpm_rom:lpm_rom_component|altrom:srom|segment0_1
- - 5 A -- MEM_SGMT 0 8 0 1 |phaserom2:34|lpm_rom:lpm_rom_component|altrom:srom|segment0_2
- - 3 A -- MEM_SGMT 0 8 0 1 |phaserom2:34|lpm_rom:lpm_rom_component|altrom:srom|segment0_3
- - 4 B -- MEM_SGMT 0 8 0 1 |phaserom2:34|lpm_rom:lpm_rom_component|altrom:srom|segment0_4
- - 1 B -- MEM_SGMT 0 8 0 1 |phaserom2:34|lpm_rom:lpm_rom_component|altrom:srom|segment0_5
- - 2 A -- MEM_SGMT 0 8 0 1 |phaserom2:34|lpm_rom:lpm_rom_component|altrom:srom|segment0_6
- - 1 C -- MEM_SGMT 0 8 0 1 |phaserom2:34|lpm_rom:lpm_rom_component|altrom:srom|segment0_7
- - 7 C -- MEM_SGMT 0 8 0 1 |phaserom3:37|lpm_rom:lpm_rom_component|altrom:srom|segment0_0
- - 4 C -- MEM_SGMT 0 8 0 1 |phaserom3:37|lpm_rom:lpm_rom_component|altrom:srom|segment0_1
- - 6 A -- MEM_SGMT 0 8 0 1 |phaserom3:37|lpm_rom:lpm_rom_component|altrom:srom|segment0_2
- - 7 B -- MEM_SGMT 0 8 0 1 |phaserom3:37|lpm_rom:lpm_rom_component|altrom:srom|segment0_3
- - 2 B -- MEM_SGMT 0 8 0 1 |phaserom3:37|lpm_rom:lpm_rom_component|altrom:srom|segment0_4
- - 6 B -- MEM_SGMT 0 8 0 1 |phaserom3:37|lpm_rom:lpm_rom_component|altrom:srom|segment0_5
- - 7 A -- MEM_SGMT 0 8 0 1 |phaserom3:37|lpm_rom:lpm_rom_component|altrom:srom|segment0_6
- - 1 A -- MEM_SGMT 0 8 0 1 |phaserom3:37|lpm_rom:lpm_rom_component|altrom:srom|segment0_7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information:d:\se\esd-5_example\dds-320-func\dds--fpga\mytest.rpt
mytest
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 24/ 96( 25%) 21/ 48( 43%) 2/ 48( 4%) 2/16( 12%) 4/16( 25%) 0/16( 0%)
B: 21/ 96( 21%) 10/ 48( 20%) 21/ 48( 43%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
C: 10/ 96( 10%) 8/ 48( 16%) 3/ 48( 6%) 4/16( 25%) 1/16( 6%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
02: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
03: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 6/24( 25%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 6/24( 25%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
14: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
16: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
17: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
18: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
19: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
20: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
21: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
22: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
23: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
24: 3/24( 12%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
EA: 4/24( 16%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information:d:\se\esd-5_example\dds-320-func\dds--fpga\mytest.rpt
mytest
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 18 PCS
DFF 17 |mainctrl:45|:65
INPUT 12 clk
Device-Specific Information:d:\se\esd-5_example\dds-320-func\dds--fpga\mytest.rpt
mytest
** EQUATIONS **
clk : INPUT;
DC : INPUT;
Mdata0 : INPUT;
Mdata1 : INPUT;
Mdata2 : INPUT;
Mdata3 : INPUT;
Mdata4 : INPUT;
Mdata5 : INPUT;
Mdata6 : INPUT;
Mdata7 : INPUT;
Mh : INPUT;
PCS : INPUT;
row0 : INPUT;
row1 : INPUT;
row2 : INPUT;
row3 : INPUT;
-- Node name is 'col0'
-- Equation name is 'col0', type is output
col0 = !_LC4_A12;
-- Node name is 'col1'
-- Equation name is 'col1', type is output
col1 = !_LC3_A12;
-- Node name is 'col2'
-- Equation name is 'col2', type is output
col2 = !_LC8_A8;
-- Node name is 'col3'
-- Equation name is 'col3', type is output
col3 = _LC6_A8;
-- Node name is 'da_cs'
-- Equation name is 'da_cs', type is output
da_cs = _LC7_A12;
-- Node name is 'da_out0'
-- Equation name is 'da_out0', type is output
da_out0 = _LC7_C22;
-- Node name is 'da_out1'
-- Equation name is 'da_out1', type is output
da_out1 = _LC2_C22;
-- Node name is 'da_out2'
-- Equation name is 'da_out2', type is output
da_out2 = _LC4_A19;
-- Node name is 'da_out3'
-- Equation name is 'da_out3', type is output
da_out3 = _LC1_A19;
-- Node name is 'da_out4'
-- Equation name is 'da_out4', type is output
da_out4 = _LC1_B18;
-- Node name is 'da_out5'
-- Equation name is 'da_out5', type is output
da_out5 = _LC4_B18;
-- Node name is 'da_out6'
-- Equation name is 'da_out6', type is output
da_out6 = _LC1_A16;
-- Node name is 'da_out7'
-- Equation name is 'da_out7', type is output
da_out7 = _LC4_A16;
-- Node name is 'da0832wr'
-- Equation name is 'da0832wr', type is output
da0832wr = _LC5_A12;
-- Node name is 'int0'
-- Equation name is 'int0', type is output
int0 = _LC2_A8;
-- Node name is 'Key0'
-- Equation name is 'Key0', type is output
Key0 = TRI(_LC1_A7, !_LC4_A8);
-- Node name is 'Key1'
-- Equation name is 'Key1', type is output
Key1 = TRI(_LC7_A2, !_LC4_A8);
-- Node name is 'Key2'
-- Equation name is 'Key2', type is output
Key2 = TRI(_LC1_A1, !_LC4_A8);
-- Node name is 'Key3'
-- Equation name is 'Key3', type is output
Key3 = TRI(_LC1_A2, !_LC4_A8);
-- Node name is '|CmdCtrl:44|:82' = '|CmdCtrl:44|M0'
-- Equation name is '_LC2_B17', type is buried
_LC2_B17 = DFFE( _EQ001, !PCS, VCC, VCC, DC);
_EQ001 = _LC2_B17 & Mh
# Mdata0 & !Mh;
-- Node name is '|CmdCtrl:44|:81' = '|CmdCtrl:44|M1'
-- Equation name is '_LC4_B22', type is buried
_LC4_B22 = DFFE( _EQ002, !PCS, VCC, VCC, DC);
_EQ002 = _LC4_B22 & Mh
# Mdata1 & !Mh;
-- Node name is '|CmdCtrl:44|:80' = '|CmdCtrl:44|M2'
-- Equation name is '_LC4_B20', type is buried
_LC4_B20 = DFFE( _EQ003, !PCS, VCC, VCC, DC);
_EQ003 = _LC4_B20 & Mh
# Mdata2 & !Mh;
-- Node name is '|CmdCtrl:44|:79' = '|CmdCtrl:44|M3'
-- Equation name is '_LC3_B20', type is buried
_LC3_B20 = DFFE( _EQ004, !PCS, VCC, VCC, DC);
_EQ004 = _LC3_B20 & Mh
# Mdata3 & !Mh;
-- Node name is '|CmdCtrl:44|:78' = '|CmdCtrl:44|M4'
-- Equation name is '_LC3_B23', type is buried
_LC3_B23 = DFFE( _EQ005, !PCS, VCC, VCC, DC);
_EQ005 = _LC3_B23 & Mh
# Mdata4 & !Mh;
-- Node name is '|CmdCtrl:44|:77' = '|CmdCtrl:44|M5'
-- Equation name is '_LC7_B20', type is buried
_LC7_B20 = DFFE( _EQ006, !PCS, VCC, VCC, DC);
_EQ006 = _LC7_B20 & Mh
# Mdata5 & !Mh;
-- Node name is '|CmdCtrl:44|:76' = '|CmdCtrl:44|M6'
-- Equation name is '_LC8_B23', type is buried
_LC8_B23 = DFFE( _EQ007, !PCS, VCC, VCC, DC);
_EQ007 = _LC8_B23 & Mh
# Mdata6 & !Mh;
-- Node name is '|CmdCtrl:44|:75' = '|CmdCtrl:44|M7'
-- Equation name is '_LC5_B11', type is buried
_LC5_B11 = DFFE( _EQ008, !PCS, VCC, VCC, DC);
_EQ008 = _LC5_B11 & Mh
# Mdata7 & !Mh;
-- Node name is '|CmdCtrl:44|:74' = '|CmdCtrl:44|M8'
-- Equation name is '_LC6_B11', type is buried
_LC6_B11 = DFFE( _EQ009, !PCS, VCC, VCC, DC);
_EQ009 = _LC6_B11 & !Mh
# Mdata0 & Mh;
-- Node name is '|CmdCtrl:44|:73' = '|CmdCtrl:44|M9'
-- Equation name is '_LC5_B22', type is buried
_LC5_B22 = DFFE( _EQ010, !PCS, VCC, VCC, DC);
_EQ010 = _LC5_B22 & !Mh
# Mdata1 & Mh;
-- Node name is '|CmdCtrl:44|:72' = '|CmdCtrl:44|M10'
-- Equation name is '_LC5_B20', type is buried
_LC5_B20 = DFFE( _EQ011, !PCS, VCC, VCC, DC);
_EQ011 = _LC5_B20 & !Mh
# Mdata2 & Mh;
-- Node name is '|CmdCtrl:44|:113'
-- Equation name is '_LC8_B22', type is buried
_LC8_B22 = DFFE( _EQ012, !PCS, VCC, VCC, VCC);
_EQ012 = DC & _LC8_B22
# !DC & Mdata1;
-- Node name is '|CmdCtrl:44|:114'
-- Equation name is '_LC2_A16', type is buried
_LC2_A16 = DFFE( _EQ013, !PCS, VCC, VCC, VCC);
_EQ013 = DC & _LC2_A16
# !DC & Mdata0;
-- Node name is '|CmdCtrl:44|:132'
-- Equation name is '_LC7_B22', type is buried
_LC7_B22 = DFFE( _EQ014, !PCS, VCC, VCC, DC);
_EQ014 = _LC7_B22 & !Mh
# Mdata7 & Mh;
-- Node name is '|CmdCtrl:44|:133'
-- Equation name is '_LC2_B22', type is buried
_LC2_B22 = DFFE( _EQ015, !PCS, VCC, VCC, DC);
_EQ015 = _LC2_B22 & !Mh
# Mdata6 & Mh;
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