📄 mytest.rpt
字号:
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GNDIO = Dedicated ground pin, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information:d:\se\esd-5_example\dds-320-func\dds--fpga\mytest.rpt
mytest
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A1 7/ 8( 87%) 1/ 8( 12%) 5/ 8( 62%) 0/2 0/2 6/22( 27%)
A2 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 0/2 0/2 9/22( 40%)
A7 2/ 8( 25%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 5/22( 22%)
A8 4/ 8( 50%) 2/ 8( 25%) 3/ 8( 37%) 0/2 0/2 4/22( 18%)
A12 8/ 8(100%) 2/ 8( 25%) 6/ 8( 75%) 1/2 0/2 2/22( 9%)
A16 5/ 8( 62%) 3/ 8( 37%) 1/ 8( 12%) 1/2 0/2 10/22( 45%)
A19 4/ 8( 50%) 2/ 8( 25%) 0/ 8( 0%) 0/2 0/2 8/22( 36%)
B11 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 2/2 0/2 8/22( 36%)
B12 8/ 8(100%) 6/ 8( 75%) 6/ 8( 75%) 1/2 0/2 3/22( 13%)
B17 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 2/2 0/2 8/22( 36%)
B18 4/ 8( 50%) 2/ 8( 25%) 0/ 8( 0%) 0/2 0/2 8/22( 36%)
B20 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 1/2 0/2 9/22( 40%)
B21 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 1/2 0/2 3/22( 13%)
B22 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 2/2 0/2 11/22( 50%)
B23 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 2/2 0/2 8/22( 36%)
C22 4/ 8( 50%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 8/22( 36%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
A25 8/8 (100%) 0/8 ( 0%) 8/8 (100%) 0/2 2/2 8/22( 36%)
B25 8/8 (100%) 2/8 ( 25%) 6/8 ( 75%) 0/2 2/2 8/22( 36%)
C25 8/8 (100%) 2/8 ( 25%) 6/8 ( 75%) 0/2 2/2 8/22( 36%)
Total dedicated input pins used: 2/6 ( 33%)
Total I/O pins used: 33/53 ( 62%)
Total logic cells used: 102/576 ( 17%)
Total embedded cells used: 24/24 (100%)
Total EABs used: 3/3 (100%)
Average fan-in: 3.44/4 ( 86%)
Total fan-in: 351/2304 ( 15%)
Total input pins required: 16
Total input I/O cell registers required: 0
Total output pins required: 19
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 102
Total flipflops required: 46
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 17/ 576 ( 2%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 7 8 0 0 0 0 2 4 0 0 0 8 8 0 0 0 5 0 0 4 0 0 0 0 0 38/8
B: 0 0 0 0 0 0 0 0 0 0 8 8 8 0 0 0 0 8 4 0 8 8 8 8 0 60/8
C: 0 0 0 0 0 0 0 0 0 0 0 0 8 0 0 0 0 0 0 0 0 0 4 0 0 4/8
Total: 7 8 0 0 0 0 2 4 0 0 8 16 24 0 0 0 5 8 4 4 8 8 12 8 0 102/24
Device-Specific Information:d:\se\esd-5_example\dds-320-func\dds--fpga\mytest.rpt
mytest
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
19 - - A -- INPUT 0 0 0 12 clk
2 - - - -- INPUT 0 0 0 18 DC
73 - - A -- INPUT 0 0 0 3 Mdata0
78 - - - 24 INPUT 0 0 0 3 Mdata1
79 - - - 24 INPUT 0 0 0 2 Mdata2
80 - - - 23 INPUT 0 0 0 2 Mdata3
81 - - - 22 INPUT 0 0 0 2 Mdata4
83 - - - 13 INPUT 0 0 0 2 Mdata5
3 - - - 12 INPUT 0 0 0 2 Mdata6
5 - - - 05 INPUT 0 0 0 2 Mdata7
84 - - - -- INPUT 0 0 0 16 Mh
7 - - - 03 INPUT 0 0 0 18 PCS
62 - - C -- INPUT 0 0 0 5 row0
61 - - C -- INPUT 0 0 0 5 row1
60 - - C -- INPUT 0 0 0 5 row2
59 - - C -- INPUT 0 0 0 5 row3
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information:d:\se\esd-5_example\dds-320-func\dds--fpga\mytest.rpt
mytest
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
67 - - B -- OUTPUT 0 1 0 0 col0
66 - - B -- OUTPUT 0 1 0 0 col1
65 - - B -- OUTPUT 0 1 0 0 col2
64 - - B -- OUTPUT 0 1 0 0 col3
69 - - A -- OUTPUT 0 1 0 0 da_cs
58 - - C -- OUTPUT 0 1 0 0 da_out0
54 - - - 21 OUTPUT 0 1 0 0 da_out1
53 - - - 20 OUTPUT 0 1 0 0 da_out2
52 - - - 19 OUTPUT 0 1 0 0 da_out3
51 - - - 18 OUTPUT 0 1 0 0 da_out4
50 - - - 17 OUTPUT 0 1 0 0 da_out5
49 - - - 16 OUTPUT 0 1 0 0 da_out6
48 - - - 15 OUTPUT 0 1 0 0 da_out7
70 - - A -- OUTPUT 0 1 0 0 da0832wr
17 - - A -- OUTPUT 0 1 0 0 int0
16 - - A -- TRI 0 1 0 0 Key0
11 - - - 01 TRI 0 1 0 0 Key1
10 - - - 01 TRI 0 1 0 0 Key2
9 - - - 02 TRI 0 1 0 0 Key3
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information:d:\se\esd-5_example\dds-320-func\dds--fpga\mytest.rpt
mytest
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 5 - B 20 DFFE 4 0 0 3 |CmdCtrl:44|M10 (|CmdCtrl:44|:72)
- 5 - B 22 DFFE 4 0 0 2 |CmdCtrl:44|M9 (|CmdCtrl:44|:73)
- 6 - B 11 DFFE 4 0 0 2 |CmdCtrl:44|M8 (|CmdCtrl:44|:74)
- 5 - B 11 DFFE 4 0 0 2 |CmdCtrl:44|M7 (|CmdCtrl:44|:75)
- 8 - B 23 DFFE 4 0 0 2 |CmdCtrl:44|M6 (|CmdCtrl:44|:76)
- 7 - B 20 DFFE 4 0 0 2 |CmdCtrl:44|M5 (|CmdCtrl:44|:77)
- 3 - B 23 DFFE 4 0 0 2 |CmdCtrl:44|M4 (|CmdCtrl:44|:78)
- 3 - B 20 DFFE 4 0 0 2 |CmdCtrl:44|M3 (|CmdCtrl:44|:79)
- 4 - B 20 DFFE 4 0 0 2 |CmdCtrl:44|M2 (|CmdCtrl:44|:80)
- 4 - B 22 DFFE 4 0 0 2 |CmdCtrl:44|M1 (|CmdCtrl:44|:81)
- 2 - B 17 DFFE 4 0 0 3 |CmdCtrl:44|M0 (|CmdCtrl:44|:82)
- 8 - B 22 DFFE 3 0 0 16 |CmdCtrl:44|:113
- 2 - A 16 DFFE 3 0 0 16 |CmdCtrl:44|:114
- 7 - B 22 DFFE 4 0 0 2 |CmdCtrl:44|:132
- 2 - B 22 DFFE 4 0 0 1 |CmdCtrl:44|:133
- 2 - B 20 DFFE 4 0 0 1 |CmdCtrl:44|:134
- 8 - B 20 DFFE 4 0 0 1 |CmdCtrl:44|:135
- 6 - B 20 DFFE 4 0 0 1 |CmdCtrl:44|:136
- 1 - A 12 DFFE 1 2 0 8 |KBSCAN:2|cnt1 (|KBSCAN:2|:15)
- 2 - A 12 DFFE 1 1 0 9 |KBSCAN:2|cnt0 (|KBSCAN:2|:16)
- 7 - A 01 AND2 4 0 0 2 |KBSCAN:2|:30
- 8 - A 01 AND2 4 0 0 5 |KBSCAN:2|:277
- 4 - A 01 AND2 4 0 0 4 |KBSCAN:2|:292
- 6 - A 01 AND2 4 0 0 6 |KBSCAN:2|:307
- 5 - A 01 AND2 4 0 0 9 |KBSCAN:2|:322
- 2 - A 07 OR2 0 2 0 1 |KBSCAN:2|:409
- 8 - A 08 AND2 0 2 1 2 |KBSCAN:2|:1009
- 3 - A 12 AND2 0 2 1 2 |KBSCAN:2|:1017
- 4 - A 12 AND2 0 2 1 2 |KBSCAN:2|:1025
- 6 - A 08 OR2 0 2 1 0 |KBSCAN:2|:1028
- 8 - A 02 OR2 s 0 4 0 2 |KBSCAN:2|~1082~1
- 1 - A 02 OR2 0 4 1 0 |KBSCAN:2|:1088
- 4 - A 02 OR2 0 4 0 1 |KBSCAN:2|:1106
- 3 - A 02 OR2 s 0 3 0 2 |KBSCAN:2|~1108~1
- 1 - A 01 OR2 0 3 1 0 |KBSCAN:2|:1112
- 2 - A 01 OR2 s 0 3 0 1 |KBSCAN:2|~1113~1
- 4 - A 08 OR2 ! 0 4 0 0 |KBSCAN:2|:1133
- 2 - A 02 OR2 s 0 4 0 2 |KBSCAN:2|~1134~1
- 5 - A 02 OR2 s 0 3 0 1 |KBSCAN:2|~1136~1
- 6 - A 02 OR2 s 0 3 0 1 |KBSCAN:2|~1136~2
- 7 - A 02 OR2 0 4 1 0 |KBSCAN:2|:1136
- 1 - A 07 OR2 0 4 1 0 |KBSCAN:2|:1160
- 2 - A 08 OR2 0 4 1 0 |KBSCAN:2|:1172
- 7 - B 21 AND2 0 4 0 2 |mainctrl:45|lpm_add_sub:117|addcore:adder|:67
- 8 - B 21 OR2 0 4 0 2 |mainctrl:45|lpm_add_sub:117|addcore:adder|:77
- 5 - B 17 OR2 0 4 0 2 |mainctrl:45|lpm_add_sub:118|addcore:adder|pcarry1
- 7 - B 17 OR2 0 3 0 2 |mainctrl:45|lpm_add_sub:118|addcore:adder|pcarry2
- 4 - B 17 OR2 0 3 0 2 |mainctrl:45|lpm_add_sub:118|addcore:adder|pcarry3
- 4 - B 23 OR2 0 3 0 2 |mainctrl:45|lpm_add_sub:118|addcore:adder|pcarry4
- 6 - B 23 OR2 0 3 0 2 |mainctrl:45|lpm_add_sub:118|addcore:adder|pcarry5
- 2 - B 23 OR2 0 3 0 2 |mainctrl:45|lpm_add_sub:118|addcore:adder|pcarry6
- 7 - B 11 OR2 0 3 0 2 |mainctrl:45|lpm_add_sub:118|addcore:adder|pcarry7
- 8 - B 11 OR2 0 3 0 2 |mainctrl:45|lpm_add_sub:118|addcore:adder|pcarry8
- 1 - B 11 OR2 0 3 0 3 |mainctrl:45|lpm_add_sub:118|addcore:adder|pcarry9
- 1 - B 12 OR2 0 3 0 3 |mainctrl:45|lpm_add_sub:118|addcore:adder|pcarry10
- 7 - B 12 AND2 0 3 0 2 |mainctrl:45|lpm_add_sub:118|addcore:adder|:147
- 1 - B 20 OR2 s ! 0 4 0 1 |mainctrl:45|~30~1
- 3 - B 22 OR2 s ! 0 4 0 2 |mainctrl:45|~30~2
- 1 - B 22 OR2 0 4 0 5 |mainctrl:45|:30
- 5 - B 21 OR2 ! 0 4 0 1 |mainctrl:45|:33
- 6 - B 22 DFFE 1 3 0 1 |mainctrl:45|devider4 (|mainctrl:45|:54)
- 4 - B 21 DFFE 1 2 0 2 |mainctrl:45|devider3 (|mainctrl:45|:55)
- 2 - B 21 DFFE 1 3 0 3 |mainctrl:45|devider2 (|mainctrl:45|:56)
- 3 - B 21 DFFE 1 2 0 5 |mainctrl:45|devider1 (|mainctrl:45|:57)
- 1 - B 21 DFFE 1 1 0 6 |mainctrl:45|devider0 (|mainctrl:45|:58)
- 6 - B 21 DFFE 1 1 0 16 |mainctrl:45|:65
- 4 - B 12 DFFE 0 4 0 24 |mainctrl:45|counter15 (|mainctrl:45|:83)
- 5 - B 12 DFFE 0 3 0 25 |mainctrl:45|counter14 (|mainctrl:45|:84)
- 3 - B 12 DFFE 0 4 0 26 |mainctrl:45|counter13 (|mainctrl:45|:85)
- 8 - B 12 DFFE 0 3 0 26 |mainctrl:45|counter12 (|mainctrl:45|:86)
- 6 - B 12 DFFE 0 4 0 27 |mainctrl:45|counter11 (|mainctrl:45|:87)
- 2 - B 12 DFFE 0 3 0 26 |mainctrl:45|counter10 (|mainctrl:45|:88)
- 2 - B 11 DFFE 0 3 0 25 |mainctrl:45|counter9 (|mainctrl:45|:89)
- 4 - B 11 DFFE 0 3 0 25 |mainctrl:45|counter8 (|mainctrl:45|:90)
- 3 - B 11 DFFE 0 3 0 1 |mainctrl:45|counter7 (|mainctrl:45|:91)
- 7 - B 23 DFFE 0 3 0 1 |mainctrl:45|counter6 (|mainctrl:45|:92)
- 5 - B 23 DFFE 0 3 0 1 |mainctrl:45|counter5 (|mainctrl:45|:93)
- 1 - B 23 DFFE 0 3 0 1 |mainctrl:45|counter4 (|mainctrl:45|:94)
- 8 - B 17 DFFE 0 3 0 1 |mainctrl:45|counter3 (|mainctrl:45|:95)
- 6 - B 17 DFFE 0 3 0 1 |mainctrl:45|counter2 (|mainctrl:45|:96)
- 1 - B 17 DFFE 0 4 0 1 |mainctrl:45|counter1 (|mainctrl:45|:97)
- 3 - B 17 DFFE 0 2 0 2 |mainctrl:45|counter0 (|mainctrl:45|:98)
- 5 - A 12 DFFE s 1 2 1 0 |mainctrl:45|cnt2~1 (|mainctrl:45|~112~1)
- 7 - A 12 DFFE 1 2 1 0 |mainctrl:45|cnt2 (|mainctrl:45|:112)
- 8 - A 12 DFFE 1 1 0 2 |mainctrl:45|cnt1 (|mainctrl:45|:113)
- 6 - A 12 DFFE 1 0 0 3 |mainctrl:45|cnt0 (|mainctrl:45|:114)
- 5 - A 16 OR2 s 0 4 0 1 |ModSel:35|~81~1
- 4 - A 16 OR2 0 4 1 0 |ModSel:35|:81
- 3 - A 16 OR2 s 0 4 0 1 |ModSel:35|~82~1
- 1 - A 16 OR2 0 4 1 0 |ModSel:35|:82
- 3 - B 18 OR2 s 0 4 0 1 |ModSel:35|~83~1
- 4 - B 18 OR2 0 4 1 0 |ModSel:35|:83
- 2 - B 18 OR2 s 0 4 0 1 |ModSel:35|~84~1
- 1 - B 18 OR2 0 4 1 0 |ModSel:35|:84
- 3 - A 19 OR2 s 0 4 0 1 |ModSel:35|~85~1
- 1 - A 19 OR2 0 4 1 0 |ModSel:35|:85
- 2 - A 19 OR2 s 0 4 0 1 |ModSel:35|~86~1
- 4 - A 19 OR2 0 4 1 0 |ModSel:35|:86
- 3 - C 22 OR2 s 0 4 0 1 |ModSel:35|~87~1
- 2 - C 22 OR2 0 4 1 0 |ModSel:35|:87
- 1 - C 22 OR2 s 0 4 0 1 |ModSel:35|~88~1
- 7 - C 22 OR2 0 4 1 0 |ModSel:35|:88
- - 5 C -- MEM_SGMT 0 8 0 1 |phaserom1:20|lpm_rom:lpm_rom_component|altrom:srom|segment0_0
- - 2 C -- MEM_SGMT 0 8 0 1 |phaserom1:20|lpm_rom:lpm_rom_component|altrom:srom|segment0_1
- - 4 A -- MEM_SGMT 0 8 0 1 |phaserom1:20|lpm_rom:lpm_rom_component|altrom:srom|segment0_2
- - 3 B -- MEM_SGMT 0 8 0 1 |phaserom1:20|lpm_rom:lpm_rom_component|altrom:srom|segment0_3
- - 5 B -- MEM_SGMT 0 8 0 1 |phaserom1:20|lpm_rom:lpm_rom_component|altrom:srom|segment0_4
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