📄 mytest.rpt
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Project Information d:\se\esd-5_example\dds-320-func\dds--fpga\mytest.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 10/10/2007 16:25:31
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
** DEVICE SUMMARY **
Chip/ Input Output Bidir Memory Memory LCs
POF Device Pins Pins Pins Bits % Utilized LCs % Utilized
mytest EPF10K10LC84-3 16 19 0 6144 100% 102 17 %
User Pins: 16 19 0
Project Information d:\se\esd-5_example\dds-320-func\dds--fpga\mytest.rpt
** PROJECT COMPILATION MESSAGES **
Warning: I/O error -- can't read initial memory content file 'G:/RESEARCH/Tjx-EXPERIMENT/ESD-5_Sample/DDS-320-func/dds--FPGA/pr.mif'-- setting all initial values to 0
Warning: I/O error -- can't read initial memory content file 'G:/RESEARCH/Tjx-EXPERIMENT/ESD-5_Sample/DDS-320-func/dds--FPGA/pr2.mif'-- setting all initial values to 0
Warning: I/O error -- can't read initial memory content file 'G:/RESEARCH/Tjx-EXPERIMENT/ESD-5_Sample/DDS-320-func/dds--FPGA/pr3.mif'-- setting all initial values to 0
Project Information d:\se\esd-5_example\dds-320-func\dds--fpga\mytest.rpt
** PIN/LOCATION/CHIP ASSIGNMENTS **
Actual
User Assignments
Assignments (if different) Node Name
mytest@19 clk
mytest@67 col0
mytest@66 col1
mytest@65 col2
mytest@64 col3
mytest@69 da_cs
mytest@58 da_out0
mytest@54 da_out1
mytest@53 da_out2
mytest@52 da_out3
mytest@51 da_out4
mytest@50 da_out5
mytest@49 da_out6
mytest@48 da_out7
mytest@70 da0832wr
mytest@2 DC
mytest@17 int0
mytest@16 Key0
mytest@11 Key1
mytest@10 Key2
mytest@9 Key3
mytest@73 Mdata0
mytest@78 Mdata1
mytest@79 Mdata2
mytest@80 Mdata3
mytest@81 Mdata4
mytest@83 Mdata5
mytest@3 Mdata6
mytest@5 Mdata7
mytest@84 Mh
mytest@7 PCS
mytest@62 row0
mytest@61 row1
mytest@60 row2
mytest@59 row3
Project Information d:\se\esd-5_example\dds-320-func\dds--fpga\mytest.rpt
** EMBEDDED ARRAYS **
|phaserom1:20|lpm_rom:lpm_rom_component|altrom:srom|content: MEMORY (
width = 8;
depth = 256;
segmentsize = 256;
mode = MEM_READONLY#MEM_INITIALIZED;
file = "G:/RESEARCH/Tjx-EXPERIMENT/ESD-5_Sample/DDS-320-func/dds--FPGA/pr.mif";
)
OF SEGMENTS (
|phaserom1:20|lpm_rom:lpm_rom_component|altrom:srom|segment0_7,
|phaserom1:20|lpm_rom:lpm_rom_component|altrom:srom|segment0_6,
|phaserom1:20|lpm_rom:lpm_rom_component|altrom:srom|segment0_5,
|phaserom1:20|lpm_rom:lpm_rom_component|altrom:srom|segment0_4,
|phaserom1:20|lpm_rom:lpm_rom_component|altrom:srom|segment0_3,
|phaserom1:20|lpm_rom:lpm_rom_component|altrom:srom|segment0_2,
|phaserom1:20|lpm_rom:lpm_rom_component|altrom:srom|segment0_1,
|phaserom1:20|lpm_rom:lpm_rom_component|altrom:srom|segment0_0
);
|phaserom2:34|lpm_rom:lpm_rom_component|altrom:srom|content: MEMORY (
width = 8;
depth = 256;
segmentsize = 256;
mode = MEM_READONLY#MEM_INITIALIZED;
file = "G:/RESEARCH/Tjx-EXPERIMENT/ESD-5_Sample/DDS-320-func/dds--FPGA/pr2.mif";
)
OF SEGMENTS (
|phaserom2:34|lpm_rom:lpm_rom_component|altrom:srom|segment0_7,
|phaserom2:34|lpm_rom:lpm_rom_component|altrom:srom|segment0_6,
|phaserom2:34|lpm_rom:lpm_rom_component|altrom:srom|segment0_5,
|phaserom2:34|lpm_rom:lpm_rom_component|altrom:srom|segment0_4,
|phaserom2:34|lpm_rom:lpm_rom_component|altrom:srom|segment0_3,
|phaserom2:34|lpm_rom:lpm_rom_component|altrom:srom|segment0_2,
|phaserom2:34|lpm_rom:lpm_rom_component|altrom:srom|segment0_1,
|phaserom2:34|lpm_rom:lpm_rom_component|altrom:srom|segment0_0
);
|phaserom3:37|lpm_rom:lpm_rom_component|altrom:srom|content: MEMORY (
width = 8;
depth = 256;
segmentsize = 256;
mode = MEM_READONLY#MEM_INITIALIZED;
file = "G:/RESEARCH/Tjx-EXPERIMENT/ESD-5_Sample/DDS-320-func/dds--FPGA/pr3.mif";
)
OF SEGMENTS (
|phaserom3:37|lpm_rom:lpm_rom_component|altrom:srom|segment0_7,
|phaserom3:37|lpm_rom:lpm_rom_component|altrom:srom|segment0_6,
|phaserom3:37|lpm_rom:lpm_rom_component|altrom:srom|segment0_5,
|phaserom3:37|lpm_rom:lpm_rom_component|altrom:srom|segment0_4,
|phaserom3:37|lpm_rom:lpm_rom_component|altrom:srom|segment0_3,
|phaserom3:37|lpm_rom:lpm_rom_component|altrom:srom|segment0_2,
|phaserom3:37|lpm_rom:lpm_rom_component|altrom:srom|segment0_1,
|phaserom3:37|lpm_rom:lpm_rom_component|altrom:srom|segment0_0
);
Project Information d:\se\esd-5_example\dds-320-func\dds--fpga\mytest.rpt
** FILE HIERARCHY **
|kbscan:2|
|kbscan:2|lpm_add_sub:44|
|kbscan:2|lpm_add_sub:44|addcore:adder|
|kbscan:2|lpm_add_sub:44|altshift:result_ext_latency_ffs|
|kbscan:2|lpm_add_sub:44|altshift:carry_ext_latency_ffs|
|kbscan:2|lpm_add_sub:44|altshift:oflow_ext_latency_ffs|
|phaserom1:20|
|phaserom1:20|lpm_rom:lpm_rom_component|
|phaserom1:20|lpm_rom:lpm_rom_component|altrom:srom|
|phaserom2:34|
|phaserom2:34|lpm_rom:lpm_rom_component|
|phaserom2:34|lpm_rom:lpm_rom_component|altrom:srom|
|modsel:35|
|phaserom3:37|
|phaserom3:37|lpm_rom:lpm_rom_component|
|phaserom3:37|lpm_rom:lpm_rom_component|altrom:srom|
|cmdctrl:44|
|mainctrl:45|
|mainctrl:45|lpm_add_sub:117|
|mainctrl:45|lpm_add_sub:117|addcore:adder|
|mainctrl:45|lpm_add_sub:117|altshift:result_ext_latency_ffs|
|mainctrl:45|lpm_add_sub:117|altshift:carry_ext_latency_ffs|
|mainctrl:45|lpm_add_sub:117|altshift:oflow_ext_latency_ffs|
|mainctrl:45|lpm_add_sub:118|
|mainctrl:45|lpm_add_sub:118|addcore:adder|
|mainctrl:45|lpm_add_sub:118|altshift:result_ext_latency_ffs|
|mainctrl:45|lpm_add_sub:118|altshift:carry_ext_latency_ffs|
|mainctrl:45|lpm_add_sub:118|altshift:oflow_ext_latency_ffs|
|mainctrl:45|lpm_add_sub:119|
|mainctrl:45|lpm_add_sub:119|addcore:adder|
|mainctrl:45|lpm_add_sub:119|altshift:result_ext_latency_ffs|
|mainctrl:45|lpm_add_sub:119|altshift:carry_ext_latency_ffs|
|mainctrl:45|lpm_add_sub:119|altshift:oflow_ext_latency_ffs|
Device-Specific Information:d:\se\esd-5_example\dds-320-func\dds--fpga\mytest.rpt
mytest
***** Logic for device 'mytest' compiled without errors.
Device: EPF10K10LC84-3
FLEX 10K Configuration Scheme: Passive Serial
Device Options:
User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable Chip_Wide Reset = OFF
Enable Chip-Wide Output Enable = OFF
Enable INIT_DONE Output = OFF
JTAG User Code = 7f
^
C
R R O
E E N
S S M V M G M G M M M M F
E E d C d N d N d d d d _ ^
K K K R R a C a D a D a a a a # D n
e e e V P V t I t I t I t t t t T O C
y y y E C E a N a D N M a N a a a a C N E
1 2 3 D S D 7 T 6 C T h 5 T 4 3 2 1 K E O
-----------------------------------------------------------------_
/ 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 |
^DATA0 | 12 74 | #TDO
^DCLK | 13 73 | Mdata0
^nCE | 14 72 | RESERVED
#TDI | 15 71 | RESERVED
Key0 | 16 70 | da0832wr
int0 | 17 69 | da_cs
RESERVED | 18 68 | GNDINT
clk | 19 67 | col0
VCCINT | 20 66 | col1
RESERVED | 21 65 | col2
RESERVED | 22 EPF10K10LC84-3 64 | col3
RESERVED | 23 63 | VCCINT
RESERVED | 24 62 | row0
RESERVED | 25 61 | row1
GNDINT | 26 60 | row2
RESERVED | 27 59 | row3
RESERVED | 28 58 | da_out0
RESERVED | 29 57 | #TMS
RESERVED | 30 56 | #TRST
^MSEL0 | 31 55 | ^nSTATUS
^MSEL1 | 32 54 | da_out1
|_ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 _|
------------------------------------------------------------------
V ^ R R R R R V G G G G V G R d d d d d d
C n E E E E E C N N N N C N E a a a a a a
C C S S S S S C D D D D C D S _ _ _ _ _ _
I O E E E E E I I I I I I I E o o o o o o
N N R R R R R N N N N N N N R u u u u u u
T F V V V V V T T T T T T T V t t t t t t
I E E E E E E 7 6 5 4 3 2
G D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
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