tiao.v

来自「DDS-320-func： 在采用 320x240 屏的设计实验箱上运行」· Verilog 代码 · 共 36 行

//产生载波信号，4KHz，正弦波
module tiao( clk, phase);
input clk;
output[7:0] phase;

reg[4:0]  	devider;
reg[15:0] 	counter;
reg[3:0]	cnt;

reg 		fc;

always @(posedge clk)
  begin
	devider=devider+1;
	if (devider==7)
		begin 
			fc=~fc;
			devider=0;
		end
  end

always @(posedge clk)
	begin
		cnt=cnt+1;
	end

always @(posedge fc)
  begin
	counter=counter+2047;
  end

assign phase[7:0]=counter[15:8];
endmodule