📄 mainctrl.rpt
字号:
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\newvhd\mytest\mainctrl.rpt
mainctrl
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 4 - B 16 AND2 0 4 0 2 |lpm_add_sub:117|addcore:adder|:67
- 2 - B 16 OR2 0 4 0 2 |lpm_add_sub:117|addcore:adder|:77
- 5 - C 19 OR2 2 2 0 2 |lpm_add_sub:118|addcore:adder|pcarry1
- 7 - C 19 OR2 1 2 0 2 |lpm_add_sub:118|addcore:adder|pcarry2
- 1 - C 19 OR2 1 2 0 2 |lpm_add_sub:118|addcore:adder|pcarry3
- 3 - C 20 OR2 1 2 0 2 |lpm_add_sub:118|addcore:adder|pcarry4
- 6 - C 20 OR2 1 2 0 2 |lpm_add_sub:118|addcore:adder|pcarry5
- 8 - C 20 OR2 1 2 0 2 |lpm_add_sub:118|addcore:adder|pcarry6
- 7 - C 18 OR2 1 2 0 2 |lpm_add_sub:118|addcore:adder|pcarry7
- 5 - C 18 OR2 1 2 0 2 |lpm_add_sub:118|addcore:adder|pcarry8
- 1 - C 22 OR2 1 2 0 2 |lpm_add_sub:118|addcore:adder|pcarry9
- 2 - C 20 OR2 1 2 0 3 |lpm_add_sub:118|addcore:adder|pcarry10
- 1 - C 18 AND2 0 3 0 3 |lpm_add_sub:118|addcore:adder|:147
- 1 - B 23 OR2 s ! 2 2 0 1 ~30~1
- 4 - B 23 OR2 s ! 1 3 0 2 ~30~2
- 2 - B 23 OR2 1 3 0 5 :30
- 1 - B 16 OR2 ! 1 3 0 1 :33
- 5 - B 23 DFFE 2 2 0 1 devider4 (:54)
- 7 - B 16 DFFE 1 2 0 2 devider3 (:55)
- 5 - B 16 DFFE 1 3 0 3 devider2 (:56)
- 3 - B 16 DFFE 1 2 0 5 devider1 (:57)
- 3 - B 23 DFFE 1 1 0 6 devider0 (:58)
- 6 - B 23 DFFE 1 1 1 16 :65
- 8 - B 16 DFFE 0 4 1 0 counter15 (:83)
- 6 - B 16 DFFE 0 3 1 1 counter14 (:84)
- 3 - C 18 DFFE 0 2 1 2 counter13 (:85)
- 2 - C 18 DFFE 0 3 1 1 counter12 (:86)
- 2 - C 19 DFFE 0 2 1 2 counter11 (:87)
- 4 - C 20 DFFE 1 2 1 1 counter10 (:88)
- 2 - C 22 DFFE 1 2 1 1 counter9 (:89)
- 6 - C 18 DFFE 1 2 1 1 counter8 (:90)
- 4 - C 18 DFFE 1 2 0 1 counter7 (:91)
- 7 - C 20 DFFE 1 2 0 1 counter6 (:92)
- 5 - C 20 DFFE 1 2 0 1 counter5 (:93)
- 1 - C 20 DFFE 1 2 0 1 counter4 (:94)
- 8 - C 19 DFFE 1 2 0 1 counter3 (:95)
- 6 - C 19 DFFE 1 2 0 1 counter2 (:96)
- 3 - C 19 DFFE 2 2 0 1 counter1 (:97)
- 4 - C 19 DFFE 1 1 0 2 counter0 (:98)
- 8 - A 24 DFFE 1 3 1 0 cnt3 (:111)
- 7 - A 24 DFFE 1 2 1 1 cnt2 (:112)
- 2 - A 24 DFFE 1 1 0 2 cnt1 (:113)
- 1 - A 24 DFFE 1 0 0 3 cnt0 (:114)
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\newvhd\mytest\mainctrl.rpt
mainctrl
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 1/ 96( 1%) 0/ 48( 0%) 2/ 48( 4%) 1/16( 6%) 2/16( 12%) 0/16( 0%)
B: 5/ 96( 5%) 0/ 48( 0%) 10/ 48( 20%) 5/16( 31%) 0/16( 0%) 0/16( 0%)
C: 6/ 96( 6%) 0/ 48( 0%) 8/ 48( 16%) 5/16( 31%) 1/16( 6%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
16: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
17: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
18: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
19: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
20: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
21: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\newvhd\mytest\mainctrl.rpt
mainctrl
** CLOCK SIGNALS **
Type Fan-out Name
DFF 18 :65
INPUT 10 clk
Device-Specific Information: d:\newvhd\mytest\mainctrl.rpt
mainctrl
** EQUATIONS **
clk : INPUT;
Div0 : INPUT;
Div1 : INPUT;
Div2 : INPUT;
Div3 : INPUT;
Div4 : INPUT;
PhaseM0 : INPUT;
PhaseM1 : INPUT;
PhaseM2 : INPUT;
PhaseM3 : INPUT;
PhaseM4 : INPUT;
PhaseM5 : INPUT;
PhaseM6 : INPUT;
PhaseM7 : INPUT;
PhaseM8 : INPUT;
PhaseM9 : INPUT;
PhaseM10 : INPUT;
-- Node name is 'clk_kb'
-- Equation name is 'clk_kb', type is output
clk_kb = cnt3;
-- Node name is ':114' = 'cnt0'
-- Equation name is 'cnt0', location is LC1_A24, type is buried.
cnt0 = DFFE(!cnt0, clk, VCC, VCC, VCC);
-- Node name is ':113' = 'cnt1'
-- Equation name is 'cnt1', location is LC2_A24, type is buried.
cnt1 = DFFE( _EQ001, clk, VCC, VCC, VCC);
_EQ001 = cnt0 & !cnt1
# !cnt0 & cnt1;
-- Node name is ':112' = 'cnt2'
-- Equation name is 'cnt2', location is LC7_A24, type is buried.
cnt2 = DFFE( _EQ002, clk, VCC, VCC, VCC);
_EQ002 = !cnt0 & cnt2
# !cnt1 & cnt2
# cnt0 & cnt1 & !cnt2;
-- Node name is ':111' = 'cnt3'
-- Equation name is 'cnt3', location is LC8_A24, type is buried.
cnt3 = DFFE( _EQ003, clk, VCC, VCC, VCC);
_EQ003 = !cnt2 & cnt3
# !cnt0 & cnt3
# !cnt1 & cnt3
# cnt0 & cnt1 & cnt2 & !cnt3;
-- Node name is ':98' = 'counter0'
-- Equation name is 'counter0', location is LC4_C19, type is buried.
counter0 = DFFE( _EQ004, _LC6_B23, VCC, VCC, VCC);
_EQ004 = counter0 & !PhaseM0
# !counter0 & PhaseM0;
-- Node name is ':97' = 'counter1'
-- Equation name is 'counter1', location is LC3_C19, type is buried.
counter1 = DFFE( _EQ005, _LC6_B23, VCC, VCC, VCC);
_EQ005 = counter0 & counter1 & PhaseM0 & PhaseM1
# !counter0 & counter1 & !PhaseM1
# counter1 & !PhaseM0 & !PhaseM1
# counter0 & !counter1 & PhaseM0 & !PhaseM1
# !counter0 & !counter1 & PhaseM1
# !counter1 & !PhaseM0 & PhaseM1;
-- Node name is ':96' = 'counter2'
-- Equation name is 'counter2', location is LC6_C19, type is buried.
counter2 = DFFE( _EQ006, _LC6_B23, VCC, VCC, VCC);
_EQ006 = counter2 & _LC5_C19 & PhaseM2
# !counter2 & _LC5_C19 & !PhaseM2
# counter2 & !_LC5_C19 & !PhaseM2
# !counter2 & !_LC5_C19 & PhaseM2;
-- Node name is ':95' = 'counter3'
-- Equation name is 'counter3', location is LC8_C19, type is buried.
counter3 = DFFE( _EQ007, _LC6_B23, VCC, VCC, VCC);
_EQ007 = counter3 & _LC7_C19 & PhaseM3
# !counter3 & _LC7_C19 & !PhaseM3
# counter3 & !_LC7_C19 & !PhaseM3
# !counter3 & !_LC7_C19 & PhaseM3;
-- Node name is ':94' = 'counter4'
-- Equation name is 'counter4', location is LC1_C20, type is buried.
counter4 = DFFE( _EQ008, _LC6_B23, VCC, VCC, VCC);
_EQ008 = counter4 & _LC1_C19 & PhaseM4
# !counter4 & _LC1_C19 & !PhaseM4
# counter4 & !_LC1_C19 & !PhaseM4
# !counter4 & !_LC1_C19 & PhaseM4;
-- Node name is ':93' = 'counter5'
-- Equation name is 'counter5', location is LC5_C20, type is buried.
counter5 = DFFE( _EQ009, _LC6_B23, VCC, VCC, VCC);
_EQ009 = counter5 & _LC3_C20 & PhaseM5
# !counter5 & _LC3_C20 & !PhaseM5
# counter5 & !_LC3_C20 & !PhaseM5
# !counter5 & !_LC3_C20 & PhaseM5;
-- Node name is ':92' = 'counter6'
-- Equation name is 'counter6', location is LC7_C20, type is buried.
counter6 = DFFE( _EQ010, _LC6_B23, VCC, VCC, VCC);
_EQ010 = counter6 & _LC6_C20 & PhaseM6
# !counter6 & _LC6_C20 & !PhaseM6
# counter6 & !_LC6_C20 & !PhaseM6
# !counter6 & !_LC6_C20 & PhaseM6;
-- Node name is ':91' = 'counter7'
-- Equation name is 'counter7', location is LC4_C18, type is buried.
counter7 = DFFE( _EQ011, _LC6_B23, VCC, VCC, VCC);
_EQ011 = counter7 & _LC8_C20 & PhaseM7
# !counter7 & _LC8_C20 & !PhaseM7
# counter7 & !_LC8_C20 & !PhaseM7
# !counter7 & !_LC8_C20 & PhaseM7;
-- Node name is ':90' = 'counter8'
-- Equation name is 'counter8', location is LC6_C18, type is buried.
counter8 = DFFE( _EQ012, _LC6_B23, VCC, VCC, VCC);
_EQ012 = counter8 & _LC7_C18 & PhaseM8
# !counter8 & _LC7_C18 & !PhaseM8
# counter8 & !_LC7_C18 & !PhaseM8
# !counter8 & !_LC7_C18 & PhaseM8;
-- Node name is ':89' = 'counter9'
-- Equation name is 'counter9', location is LC2_C22, type is buried.
counter9 = DFFE( _EQ013, _LC6_B23, VCC, VCC, VCC);
_EQ013 = counter9 & _LC5_C18 & PhaseM9
# !counter9 & _LC5_C18 & !PhaseM9
# counter9 & !_LC5_C18 & !PhaseM9
# !counter9 & !_LC5_C18 & PhaseM9;
-- Node name is ':88' = 'counter10'
-- Equation name is 'counter10', location is LC4_C20, type is buried.
counter10 = DFFE( _EQ014, _LC6_B23, VCC, VCC, VCC);
_EQ014 = counter10 & _LC1_C22 & PhaseM10
# !counter10 & _LC1_C22 & !PhaseM10
# counter10 & !_LC1_C22 & !PhaseM10
# !counter10 & !_LC1_C22 & PhaseM10;
-- Node name is ':87' = 'counter11'
-- Equation name is 'counter11', location is LC2_C19, type is buried.
counter11 = DFFE( _EQ015, _LC6_B23, VCC, VCC, VCC);
_EQ015 = counter11 & !_LC2_C20
# !counter11 & _LC2_C20;
-- Node name is ':86' = 'counter12'
-- Equation name is 'counter12', location is LC2_C18, type is buried.
counter12 = DFFE( _EQ016, _LC6_B23, VCC, VCC, VCC);
_EQ016 = !counter11 & counter12
# counter12 & !_LC2_C20
# counter11 & !counter12 & _LC2_C20;
-- Node name is ':85' = 'counter13'
-- Equation name is 'counter13', location is LC3_C18, type is buried.
counter13 = DFFE( _EQ017, _LC6_B23, VCC, VCC, VCC);
_EQ017 = counter13 & !_LC1_C18
# !counter13 & _LC1_C18;
-- Node name is ':84' = 'counter14'
-- Equation name is 'counter14', location is LC6_B16, type is buried.
counter14 = DFFE( _EQ018, _LC6_B23, VCC, VCC, VCC);
_EQ018 = !counter13 & counter14
# counter14 & !_LC1_C18
# counter13 & !counter14 & _LC1_C18;
-- Node name is ':83' = 'counter15'
-- Equation name is 'counter15', location is LC8_B16, type is buried.
counter15 = DFFE( _EQ019, _LC6_B23, VCC, VCC, VCC);
_EQ019 = !counter13 & counter15
# counter15 & !_LC1_C18
# !counter14 & counter15
# counter13 & counter14 & !counter15 & _LC1_C18;
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -