📄 mytest.rpt
字号:
- 5 - C 23 OR2 0 4 0 2 |mainctrl:45|lpm_add_sub:118|addcore:adder|pcarry1
- 1 - C 14 OR2 0 3 0 2 |mainctrl:45|lpm_add_sub:118|addcore:adder|pcarry2
- 5 - B 15 OR2 0 3 0 2 |mainctrl:45|lpm_add_sub:118|addcore:adder|pcarry3
- 1 - B 15 OR2 0 3 0 2 |mainctrl:45|lpm_add_sub:118|addcore:adder|pcarry4
- 5 - B 19 OR2 0 3 0 2 |mainctrl:45|lpm_add_sub:118|addcore:adder|pcarry5
- 3 - B 17 OR2 0 3 0 2 |mainctrl:45|lpm_add_sub:118|addcore:adder|pcarry6
- 4 - B 17 OR2 0 3 0 2 |mainctrl:45|lpm_add_sub:118|addcore:adder|pcarry7
- 6 - C 15 OR2 0 3 0 2 |mainctrl:45|lpm_add_sub:118|addcore:adder|pcarry8
- 1 - C 23 OR2 0 3 0 3 |mainctrl:45|lpm_add_sub:118|addcore:adder|pcarry9
- 2 - C 01 OR2 0 3 0 3 |mainctrl:45|lpm_add_sub:118|addcore:adder|pcarry10
- 7 - C 01 AND2 0 3 0 2 |mainctrl:45|lpm_add_sub:118|addcore:adder|:147
- 1 - B 24 OR2 s ! 0 4 0 1 |mainctrl:45|~30~1
- 2 - B 20 OR2 s ! 0 4 0 2 |mainctrl:45|~30~2
- 8 - B 20 OR2 0 4 0 5 |mainctrl:45|:30
- 2 - B 24 OR2 ! 0 4 0 1 |mainctrl:45|:33
- 3 - B 20 DFFE 1 3 0 1 |mainctrl:45|devider4 (|mainctrl:45|:54)
- 7 - B 24 DFFE 1 2 0 2 |mainctrl:45|devider3 (|mainctrl:45|:55)
- 3 - B 24 DFFE 1 3 0 3 |mainctrl:45|devider2 (|mainctrl:45|:56)
- 4 - B 24 DFFE 1 2 0 5 |mainctrl:45|devider1 (|mainctrl:45|:57)
- 8 - B 24 DFFE 1 1 0 6 |mainctrl:45|devider0 (|mainctrl:45|:58)
- 7 - B 20 DFFE 1 1 0 16 |mainctrl:45|:65
- 6 - C 01 DFFE 0 4 0 7 |mainctrl:45|counter15 (|mainctrl:45|:83)
- 4 - C 01 DFFE 0 3 0 8 |mainctrl:45|counter14 (|mainctrl:45|:84)
- 5 - C 01 DFFE 0 4 0 9 |mainctrl:45|counter13 (|mainctrl:45|:85)
- 3 - C 01 DFFE 0 3 0 9 |mainctrl:45|counter12 (|mainctrl:45|:86)
- 1 - C 01 DFFE 0 4 0 10 |mainctrl:45|counter11 (|mainctrl:45|:87)
- 8 - C 01 DFFE 0 3 0 9 |mainctrl:45|counter10 (|mainctrl:45|:88)
- 2 - C 23 DFFE 0 3 0 8 |mainctrl:45|counter9 (|mainctrl:45|:89)
- 2 - C 15 DFFE 0 3 0 8 |mainctrl:45|counter8 (|mainctrl:45|:90)
- 5 - B 17 DFFE 0 3 0 1 |mainctrl:45|counter7 (|mainctrl:45|:91)
- 1 - B 17 DFFE 0 3 0 1 |mainctrl:45|counter6 (|mainctrl:45|:92)
- 2 - B 19 DFFE 0 3 0 1 |mainctrl:45|counter5 (|mainctrl:45|:93)
- 6 - B 15 DFFE 0 3 0 1 |mainctrl:45|counter4 (|mainctrl:45|:94)
- 3 - B 15 DFFE 0 3 0 1 |mainctrl:45|counter3 (|mainctrl:45|:95)
- 3 - C 14 DFFE 0 3 0 1 |mainctrl:45|counter2 (|mainctrl:45|:96)
- 3 - C 23 DFFE 0 4 0 1 |mainctrl:45|counter1 (|mainctrl:45|:97)
- 7 - C 23 DFFE 0 2 0 2 |mainctrl:45|counter0 (|mainctrl:45|:98)
- 8 - A 24 DFFE s 1 2 1 0 |mainctrl:45|cnt2~1 (|mainctrl:45|~112~1)
- 7 - A 24 DFFE 1 2 1 0 |mainctrl:45|cnt2 (|mainctrl:45|:112)
- 2 - A 24 DFFE 1 1 0 2 |mainctrl:45|cnt1 (|mainctrl:45|:113)
- 1 - A 24 DFFE 1 0 0 3 |mainctrl:45|cnt0 (|mainctrl:45|:114)
- 1 - C 15 AND2 0 3 1 0 |ModSel:80|:46
- 5 - C 15 OR2 0 4 1 0 |ModSel:80|:67
- 2 - C 17 OR2 0 4 1 0 |ModSel:80|:68
- 1 - C 18 OR2 0 4 1 0 |ModSel:80|:69
- 3 - C 19 OR2 0 4 1 0 |ModSel:80|:70
- 6 - C 19 OR2 0 4 1 0 |ModSel:80|:71
- 4 - C 21 OR2 0 4 1 0 |ModSel:80|:72
- 7 - C 19 OR2 0 4 1 0 |ModSel:80|:73
- 4 - A 20 AND2 s 0 4 0 1 |phaserom1:20|lpm_rom:lpm_rom_component|altrom:srom|segment0_1~1
- - 4 C -- MEM_SGMT 0 8 0 14 |phaserom1:20|lpm_rom:lpm_rom_component|altrom:srom|segment0_1
- - 3 C -- MEM_SGMT 0 8 0 14 |phaserom1:20|lpm_rom:lpm_rom_component|altrom:srom|segment0_2
- - 5 C -- MEM_SGMT 0 8 0 17 |phaserom1:20|lpm_rom:lpm_rom_component|altrom:srom|segment0_3
- 6 - A 23 OR2 s 0 4 0 1 |phaserom1:20|lpm_rom:lpm_rom_component|altrom:srom|segment0_4~1
- - 2 C -- MEM_SGMT 0 8 0 13 |phaserom1:20|lpm_rom:lpm_rom_component|altrom:srom|segment0_4
- 6 - A 16 OR2 s 0 4 0 1 |phaserom1:20|lpm_rom:lpm_rom_component|altrom:srom|segment0_5~1
- - 8 C -- MEM_SGMT 0 8 0 14 |phaserom1:20|lpm_rom:lpm_rom_component|altrom:srom|segment0_5
- 8 - A 14 OR2 s 0 4 0 1 |phaserom1:20|lpm_rom:lpm_rom_component|altrom:srom|segment0_6~1
- - 6 C -- MEM_SGMT 0 8 0 14 |phaserom1:20|lpm_rom:lpm_rom_component|altrom:srom|segment0_6
- 7 - C 15 OR2 s 0 4 0 1 |phaserom1:20|lpm_rom:lpm_rom_component|altrom:srom|segment0_7~1
- - 1 C -- MEM_SGMT 0 8 0 14 |phaserom1:20|lpm_rom:lpm_rom_component|altrom:srom|segment0_7
- - 3 A -- MEM_SGMT 0 8 0 8 |phaserom2:69|lpm_rom:lpm_rom_component|altrom:srom|segment0_0
- - 8 A -- MEM_SGMT 0 8 0 12 |phaserom2:69|lpm_rom:lpm_rom_component|altrom:srom|segment0_1
- - 7 A -- MEM_SGMT 0 8 0 20 |phaserom2:69|lpm_rom:lpm_rom_component|altrom:srom|segment0_2
- - 1 A -- MEM_SGMT 0 8 0 14 |phaserom2:69|lpm_rom:lpm_rom_component|altrom:srom|segment0_3
- - 5 A -- MEM_SGMT 0 8 0 15 |phaserom2:69|lpm_rom:lpm_rom_component|altrom:srom|segment0_4
- 1 - A 17 AND2 s 0 3 0 2 |phaserom2:69|lpm_rom:lpm_rom_component|altrom:srom|segment0_5~1
- - 6 A -- MEM_SGMT 0 8 0 16 |phaserom2:69|lpm_rom:lpm_rom_component|altrom:srom|segment0_5
- - 4 A -- MEM_SGMT 0 8 0 12 |phaserom2:69|lpm_rom:lpm_rom_component|altrom:srom|segment0_6
- - 2 A -- MEM_SGMT 0 8 0 8 |phaserom2:69|lpm_rom:lpm_rom_component|altrom:srom|segment0_7
- 1 - B 12 AND2 0 2 0 1 |tiao:47|lpm_add_sub:88|addcore:adder|:59
- 5 - B 06 AND2 0 3 0 1 |tiao:47|lpm_add_sub:88|addcore:adder|:63
- 1 - A 11 OR2 0 4 0 4 |tiao:47|lpm_add_sub:89|addcore:adder|pcarry3
- 6 - A 08 OR2 0 4 0 4 |tiao:47|lpm_add_sub:89|addcore:adder|pcarry6
- 5 - A 08 OR2 0 4 0 4 |tiao:47|lpm_add_sub:89|addcore:adder|pcarry9
- 8 - A 07 OR2 0 4 0 3 |tiao:47|lpm_add_sub:89|addcore:adder|:147
- 4 - B 06 AND2 s ! 0 3 0 3 |tiao:47|~11~1
- 1 - B 06 AND2 0 3 0 4 |tiao:47|:11
- 6 - B 06 DFFE 1 3 0 1 |tiao:47|devider4 (|tiao:47|:35)
- 7 - B 06 DFFE 1 3 0 2 |tiao:47|devider3 (|tiao:47|:36)
- 8 - B 06 DFFE 1 3 0 3 |tiao:47|devider2 (|tiao:47|:37)
- 2 - B 06 DFFE 1 2 0 5 |tiao:47|devider1 (|tiao:47|:38)
- 3 - B 06 DFFE 1 2 0 5 |tiao:47|devider0 (|tiao:47|:39)
- 1 - A 07 DFFE 1 1 0 16 |tiao:47|fc (|tiao:47|:46)
- 5 - A 07 DFFE 0 4 0 8 |tiao:47|counter15 (|tiao:47|:64)
- 2 - A 07 DFFE 0 3 0 9 |tiao:47|counter14 (|tiao:47|:65)
- 3 - A 07 DFFE 0 2 0 10 |tiao:47|counter13 (|tiao:47|:66)
- 4 - A 07 DFFE 0 4 0 9 |tiao:47|counter12 (|tiao:47|:67)
- 6 - A 07 DFFE 0 3 0 10 |tiao:47|counter11 (|tiao:47|:68)
- 7 - A 07 DFFE 0 2 0 11 |tiao:47|counter10 (|tiao:47|:69)
- 8 - A 08 DFFE 0 4 0 9 |tiao:47|counter9 (|tiao:47|:70)
- 1 - A 08 DFFE 0 3 0 10 |tiao:47|counter8 (|tiao:47|:71)
- 7 - A 08 DFFE 0 2 0 3 |tiao:47|counter7 (|tiao:47|:72)
- 4 - A 08 DFFE 0 4 0 1 |tiao:47|counter6 (|tiao:47|:73)
- 3 - A 08 DFFE 0 3 0 2 |tiao:47|counter5 (|tiao:47|:74)
- 2 - A 08 DFFE 0 2 0 3 |tiao:47|counter4 (|tiao:47|:75)
- 5 - A 11 DFFE 0 4 0 1 |tiao:47|counter3 (|tiao:47|:76)
- 4 - A 11 DFFE 0 3 0 2 |tiao:47|counter2 (|tiao:47|:77)
- 3 - A 11 DFFE 0 2 0 3 |tiao:47|counter1 (|tiao:47|:78)
- 2 - A 11 DFFE 0 1 0 4 |tiao:47|counter0 (|tiao:47|:79)
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: e:\esd-5_sample\dds-128-modu\verilog\mytest.rpt
mytest
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 20/ 96( 20%) 13/ 48( 27%) 43/ 48( 89%) 2/16( 12%) 4/16( 25%) 0/16( 0%)
B: 13/ 96( 13%) 13/ 48( 27%) 16/ 48( 33%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
C: 28/ 96( 29%) 6/ 48( 12%) 33/ 48( 68%) 4/16( 25%) 1/16( 6%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 3/24( 12%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
02: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
03: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
06: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
13: 3/24( 12%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
14: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
16: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
17: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
18: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
19: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
20: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
21: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
22: 5/24( 20%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
23: 3/24( 12%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
24: 5/24( 20%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
EA: 13/24( 54%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\esd-5_sample\dds-128-modu\verilog\mytest.rpt
mytest
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 26 clk
INPUT 18 PCS
DFF 17 |mainctrl:45|:65
DFF 17 |tiao:47|fc
Device-Specific Information: e:\esd-5_sample\dds-128-modu\verilog\mytest.rpt
mytest
** EQUATIONS **
clk : INPUT;
DC : INPUT;
Mdata0 : INPUT;
Mdata1 : INPUT;
Mdata2 : INPUT;
Mdata3 : INPUT;
Mdata4 : INPUT;
Mdata5 : INPUT;
Mdata6 : INPUT;
Mdata7 : INPUT;
Mh : INPUT;
PCS : INPUT;
row0 : INPUT;
row1 : INPUT;
row2 : INPUT;
row3 : INPUT;
-- Node name is 'col0'
-- Equation name is 'col0', type is output
col0 = !_LC1_B3;
-- Node name is 'col1'
-- Equation name is 'col1', type is output
col1 = !_LC3_B3;
-- Node name is 'col2'
-- Equation name is 'col2', type is output
col2 = !_LC5_B3;
-- Node name is 'col3'
-- Equation name is 'col3', type is output
col3 = _LC7_B3;
-- Node name is 'da_cs'
-- Equation name is 'da_cs', type is output
da_cs = _LC7_A24;
-- Node name is 'da_out0'
-- Equation name is 'da_out0', type is output
da_out0 = _LC7_C19;
-- Node name is 'da_out1'
-- Equation name is 'da_out1', type is output
da_out1 = _LC4_C21;
-- Node name is 'da_out2'
-- Equation name is 'da_out2', type is output
da_out2 = _LC6_C19;
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