📄 mytest.rpt
字号:
7 - - - 03 INPUT 0 0 0 18 PCS
62 - - C -- INPUT 0 0 0 5 row0
61 - - C -- INPUT 0 0 0 5 row1
60 - - C -- INPUT 0 0 0 5 row2
59 - - C -- INPUT 0 0 0 5 row3
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\esd-5_sample\dds-128-modu\verilog\mytest.rpt
mytest
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
67 - - B -- OUTPUT 0 1 0 0 col0
66 - - B -- OUTPUT 0 1 0 0 col1
65 - - B -- OUTPUT 0 1 0 0 col2
64 - - B -- OUTPUT 0 1 0 0 col3
69 - - A -- OUTPUT 0 1 0 0 da_cs
58 - - C -- OUTPUT 0 1 0 0 da_out0
54 - - - 21 OUTPUT 0 1 0 0 da_out1
53 - - - 20 OUTPUT 0 1 0 0 da_out2
52 - - - 19 OUTPUT 0 1 0 0 da_out3
51 - - - 18 OUTPUT 0 1 0 0 da_out4
50 - - - 17 OUTPUT 0 1 0 0 da_out5
49 - - - 16 OUTPUT 0 1 0 0 da_out6
48 - - - 15 OUTPUT 0 1 0 0 da_out7
70 - - A -- OUTPUT 0 1 0 0 da0832wr
17 - - A -- OUTPUT 0 1 0 0 int0
16 - - A -- TRI 0 1 0 0 Key0
11 - - - 01 TRI 0 1 0 0 Key1
10 - - - 01 TRI 0 1 0 0 Key2
9 - - - 02 TRI 0 1 0 0 Key3
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\esd-5_sample\dds-128-modu\verilog\mytest.rpt
mytest
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 2 - A 18 OR2 0 4 0 2 |CHENGFA2:72|one_bit_adder:U_0_1|:15
- 6 - A 18 OR2 0 4 0 3 |CHENGFA2:72|one_bit_adder:U_0_2|:8
- 4 - A 18 OR2 0 4 0 2 |CHENGFA2:72|one_bit_adder:U_0_2|:15
- 3 - A 18 OR2 0 2 0 3 |CHENGFA2:72|one_bit_adder:U_0_3|:8
- 3 - A 19 OR2 0 4 0 5 |CHENGFA2:72|one_bit_adder:U_0_3|:13
- 1 - A 18 OR2 0 4 0 3 |CHENGFA2:72|one_bit_adder:U_0_3|:15
- 2 - A 20 OR2 0 2 0 3 |CHENGFA2:72|one_bit_adder:U_0_4|:8
- 7 - A 17 OR2 0 3 0 3 |CHENGFA2:72|one_bit_adder:U_0_4|:13
- 1 - A 20 OR2 0 4 0 3 |CHENGFA2:72|one_bit_adder:U_0_5|:8
- 7 - A 20 OR2 0 4 0 3 |CHENGFA2:72|one_bit_adder:U_0_5|:13
- 3 - A 20 OR2 0 4 0 1 |CHENGFA2:72|one_bit_adder:U_0_5|:14
- 5 - A 20 OR2 0 2 0 2 |CHENGFA2:72|one_bit_adder:U_0_5|:15
- 8 - A 20 OR2 0 3 0 3 |CHENGFA2:72|one_bit_adder:U_0_6|:8
- 4 - A 17 OR2 s 0 4 0 3 |CHENGFA2:72|one_bit_adder:U_1_0|~12~1
- 1 - A 15 OR2 s 0 3 0 1 |CHENGFA2:72|one_bit_adder:U_1_1|~8~1
- 1 - A 21 OR2 0 4 0 2 |CHENGFA2:72|one_bit_adder:U_1_1|:15
- 6 - A 21 OR2 0 4 0 2 |CHENGFA2:72|one_bit_adder:U_1_2|:8
- 2 - A 21 OR2 0 4 0 2 |CHENGFA2:72|one_bit_adder:U_1_2|:15
- 3 - A 21 OR2 0 4 0 2 |CHENGFA2:72|one_bit_adder:U_1_3|:8
- 4 - A 21 OR2 0 4 0 2 |CHENGFA2:72|one_bit_adder:U_1_3|:15
- 1 - A 13 OR2 0 4 0 2 |CHENGFA2:72|one_bit_adder:U_1_4|:8
- 3 - A 13 OR2 0 4 0 2 |CHENGFA2:72|one_bit_adder:U_1_4|:15
- 8 - A 13 OR2 0 3 0 2 |CHENGFA2:72|one_bit_adder:U_1_5|:8
- 6 - A 13 OR2 0 3 0 3 |CHENGFA2:72|one_bit_adder:U_1_5|:15
- 6 - A 20 OR2 0 4 0 4 |CHENGFA2:72|one_bit_adder:U_1_6|:13
- 5 - A 19 OR2 s 0 4 0 1 |CHENGFA2:72|one_bit_adder:U_1_6|~15~1
- 6 - A 19 OR2 s 0 4 0 1 |CHENGFA2:72|one_bit_adder:U_1_6|~15~2
- 7 - A 19 OR2 s 0 4 0 1 |CHENGFA2:72|one_bit_adder:U_1_6|~15~3
- 2 - A 19 OR2 s 0 4 0 1 |CHENGFA2:72|one_bit_adder:U_1_6|~15~4
- 3 - A 23 AND2 s 0 4 0 1 |CHENGFA2:72|one_bit_adder:U_1_6|~15~5
- 3 - A 15 OR2 0 4 0 2 |CHENGFA2:72|one_bit_adder:U_2_0|:12
- 4 - A 15 OR2 s 0 3 0 1 |CHENGFA2:72|one_bit_adder:U_2_1|~8~1
- 2 - A 15 OR2 0 4 0 2 |CHENGFA2:72|one_bit_adder:U_2_1|:15
- 1 - A 16 OR2 0 4 0 2 |CHENGFA2:72|one_bit_adder:U_2_2|:8
- 2 - A 16 OR2 0 4 0 2 |CHENGFA2:72|one_bit_adder:U_2_2|:15
- 4 - A 16 OR2 0 4 0 2 |CHENGFA2:72|one_bit_adder:U_2_3|:8
- 3 - A 16 OR2 0 4 0 2 |CHENGFA2:72|one_bit_adder:U_2_3|:15
- 8 - A 16 OR2 0 4 0 2 |CHENGFA2:72|one_bit_adder:U_2_4|:8
- 5 - A 16 OR2 0 4 0 3 |CHENGFA2:72|one_bit_adder:U_2_4|:15
- 4 - A 23 OR2 0 4 0 3 |CHENGFA2:72|one_bit_adder:U_2_5|:13
- 8 - A 23 OR2 0 3 0 2 |CHENGFA2:72|one_bit_adder:U_2_5|:15
- 1 - A 23 OR2 0 2 0 2 |CHENGFA2:72|one_bit_adder:U_2_6|:8
- 5 - A 23 OR2 0 4 0 2 |CHENGFA2:72|one_bit_adder:U_2_6|:13
- 3 - A 17 OR2 s 0 4 0 3 |CHENGFA2:72|one_bit_adder:U_2_6|~15~1
- 5 - A 21 OR2 s 0 4 0 1 |CHENGFA2:72|one_bit_adder:U_2_6|~15~2
- 7 - A 21 OR2 s 0 4 0 1 |CHENGFA2:72|one_bit_adder:U_2_6|~15~3
- 8 - A 21 OR2 s 0 4 0 1 |CHENGFA2:72|one_bit_adder:U_2_6|~15~4
- 4 - A 13 OR2 s 0 4 0 1 |CHENGFA2:72|one_bit_adder:U_2_6|~15~5
- 5 - A 13 OR2 s 0 4 0 1 |CHENGFA2:72|one_bit_adder:U_2_6|~15~6
- 5 - A 18 OR2 s 0 4 0 1 |CHENGFA2:72|one_bit_adder:U_2_6|~15~7
- 7 - A 18 OR2 s 0 4 0 1 |CHENGFA2:72|one_bit_adder:U_2_6|~15~8
- 8 - A 19 OR2 s 0 4 0 1 |CHENGFA2:72|one_bit_adder:U_2_6|~15~9
- 1 - A 19 OR2 s 0 4 0 1 |CHENGFA2:72|one_bit_adder:U_2_6|~15~10
- 8 - A 18 OR2 s 0 4 0 1 |CHENGFA2:72|one_bit_adder:U_2_6|~15~11
- 7 - A 13 OR2 s 0 4 0 1 |CHENGFA2:72|one_bit_adder:U_2_6|~15~12
- 7 - A 23 OR2 0 4 0 2 |CHENGFA2:72|one_bit_adder:U_2_6|:15
- 6 - A 15 OR2 0 4 0 2 |CHENGFA2:72|one_bit_adder:U_3_0|:12
- 8 - A 15 OR2 s 0 3 0 1 |CHENGFA2:72|one_bit_adder:U_3_1|~8~1
- 5 - A 15 OR2 0 4 0 2 |CHENGFA2:72|one_bit_adder:U_3_1|:15
- 3 - A 14 OR2 0 4 0 2 |CHENGFA2:72|one_bit_adder:U_3_2|:8
- 4 - A 14 OR2 0 4 0 2 |CHENGFA2:72|one_bit_adder:U_3_2|:15
- 5 - A 14 OR2 0 4 0 2 |CHENGFA2:72|one_bit_adder:U_3_3|:8
- 7 - A 14 OR2 0 4 0 3 |CHENGFA2:72|one_bit_adder:U_3_3|:15
- 7 - A 16 OR2 0 4 0 3 |CHENGFA2:72|one_bit_adder:U_3_4|:13
- 6 - A 14 OR2 0 3 0 2 |CHENGFA2:72|one_bit_adder:U_3_4|:15
- 1 - C 22 OR2 0 4 0 2 |CHENGFA2:72|one_bit_adder:U_3_5|:8
- 6 - C 22 OR2 0 4 0 2 |CHENGFA2:72|one_bit_adder:U_3_5|:15
- 7 - C 22 OR2 0 4 0 2 |CHENGFA2:72|one_bit_adder:U_3_6|:8
- 4 - C 22 OR2 0 4 0 2 |CHENGFA2:72|one_bit_adder:U_3_6|:15
- 7 - A 15 OR2 0 4 0 2 |CHENGFA2:72|one_bit_adder:U_4_0|:12
- 3 - A 22 OR2 s 0 3 0 1 |CHENGFA2:72|one_bit_adder:U_4_1|~8~1
- 5 - A 22 OR2 0 4 0 2 |CHENGFA2:72|one_bit_adder:U_4_1|:15
- 7 - A 22 OR2 0 4 0 2 |CHENGFA2:72|one_bit_adder:U_4_2|:8
- 1 - A 22 OR2 0 4 0 3 |CHENGFA2:72|one_bit_adder:U_4_2|:15
- 2 - A 14 OR2 0 4 0 3 |CHENGFA2:72|one_bit_adder:U_4_3|:13
- 1 - A 14 OR2 0 3 0 2 |CHENGFA2:72|one_bit_adder:U_4_3|:15
- 8 - C 22 OR2 0 4 0 2 |CHENGFA2:72|one_bit_adder:U_4_4|:8
- 3 - C 22 OR2 0 4 0 2 |CHENGFA2:72|one_bit_adder:U_4_4|:15
- 2 - C 22 OR2 0 4 0 2 |CHENGFA2:72|one_bit_adder:U_4_5|:8
- 5 - C 22 OR2 0 4 0 2 |CHENGFA2:72|one_bit_adder:U_4_5|:15
- 7 - C 17 OR2 0 4 0 2 |CHENGFA2:72|one_bit_adder:U_4_6|:8
- 3 - C 17 OR2 0 4 0 2 |CHENGFA2:72|one_bit_adder:U_4_6|:15
- 4 - A 22 OR2 0 4 0 2 |CHENGFA2:72|one_bit_adder:U_5_0|:12
- 6 - A 22 OR2 0 4 0 4 |CHENGFA2:72|one_bit_adder:U_5_1|:8
- 2 - A 22 OR2 0 4 0 4 |CHENGFA2:72|one_bit_adder:U_5_1|:15
- 4 - C 20 OR2 0 2 0 1 |CHENGFA2:72|one_bit_adder:U_5_2|:8
- 4 - C 15 OR2 0 4 0 4 |CHENGFA2:72|one_bit_adder:U_5_2|:13
- 6 - C 20 OR2 0 3 0 2 |CHENGFA2:72|one_bit_adder:U_5_2|:15
- 7 - C 20 OR2 0 4 0 2 |CHENGFA2:72|one_bit_adder:U_5_3|:8
- 8 - C 20 OR2 0 4 0 2 |CHENGFA2:72|one_bit_adder:U_5_3|:15
- 4 - C 18 OR2 0 4 0 3 |CHENGFA2:72|one_bit_adder:U_5_4|:8
- 6 - C 18 OR2 0 4 0 2 |CHENGFA2:72|one_bit_adder:U_5_4|:15
- 7 - C 18 OR2 0 4 0 2 |CHENGFA2:72|one_bit_adder:U_5_5|:8
- 2 - C 18 OR2 0 4 0 2 |CHENGFA2:72|one_bit_adder:U_5_5|:15
- 5 - C 17 OR2 0 4 0 3 |CHENGFA2:72|one_bit_adder:U_5_6|:8
- 8 - C 17 OR2 ! 0 4 0 2 |CHENGFA2:72|one_bit_adder:U_5_6|:15
- 4 - A 19 AND2 0 2 0 6 |CHENGFA2:72|:5201
- 2 - A 17 AND2 0 2 0 4 |CHENGFA2:72|:5430
- 5 - A 17 AND2 0 2 0 4 |CHENGFA2:72|:5487
- 2 - A 13 AND2 0 2 0 3 |CHENGFA2:72|:5740
- 2 - A 23 AND2 0 2 0 2 |CHENGFA2:72|:5993
- 2 - C 14 DFFE 4 0 0 3 |CmdCtrl:44|M10 (|CmdCtrl:44|:72)
- 8 - C 23 DFFE 4 0 0 2 |CmdCtrl:44|M9 (|CmdCtrl:44|:73)
- 8 - C 15 DFFE 4 0 0 2 |CmdCtrl:44|M8 (|CmdCtrl:44|:74)
- 6 - B 17 DFFE 4 0 0 2 |CmdCtrl:44|M7 (|CmdCtrl:44|:75)
- 2 - B 17 DFFE 4 0 0 2 |CmdCtrl:44|M6 (|CmdCtrl:44|:76)
- 3 - B 19 DFFE 4 0 0 2 |CmdCtrl:44|M5 (|CmdCtrl:44|:77)
- 7 - B 15 DFFE 4 0 0 2 |CmdCtrl:44|M4 (|CmdCtrl:44|:78)
- 4 - B 15 DFFE 4 0 0 2 |CmdCtrl:44|M3 (|CmdCtrl:44|:79)
- 4 - C 14 DFFE 4 0 0 2 |CmdCtrl:44|M2 (|CmdCtrl:44|:80)
- 4 - C 23 DFFE 4 0 0 2 |CmdCtrl:44|M1 (|CmdCtrl:44|:81)
- 6 - C 23 DFFE 4 0 0 3 |CmdCtrl:44|M0 (|CmdCtrl:44|:82)
- 1 - C 19 DFFE 3 0 0 8 |CmdCtrl:44|:113
- 3 - C 15 DFFE 3 0 0 8 |CmdCtrl:44|:114
- 4 - B 20 DFFE 4 0 0 2 |CmdCtrl:44|:132
- 1 - B 20 DFFE 4 0 0 1 |CmdCtrl:44|:133
- 1 - B 19 DFFE 4 0 0 1 |CmdCtrl:44|:134
- 2 - B 15 DFFE 4 0 0 1 |CmdCtrl:44|:135
- 8 - B 15 DFFE 4 0 0 1 |CmdCtrl:44|:136
- 5 - C 20 OR2 0 4 0 3 |HUAN:75|LPM_ADD_SUB:139|addcore:adder|:125
- 3 - C 18 AND2 0 3 0 3 |HUAN:75|LPM_ADD_SUB:139|addcore:adder|:133
- 1 - C 17 DFFE 1 4 0 1 |HUAN:75|:18
- 4 - C 17 DFFE 1 4 0 1 |HUAN:75|:20
- 6 - C 17 DFFE 1 3 0 1 |HUAN:75|:22
- 8 - C 18 DFFE 1 4 0 1 |HUAN:75|:24
- 5 - C 18 DFFE 1 3 0 1 |HUAN:75|:26
- 1 - C 20 DFFE 1 4 0 1 |HUAN:75|:28
- 2 - C 20 DFFE 1 4 0 1 |HUAN:75|:30
- 3 - C 20 DFFE 1 2 0 1 |HUAN:75|:32
- 4 - B 03 DFFE 1 2 0 5 |KBSCAN:81|cnt1 (|KBSCAN:81|:15)
- 2 - B 03 DFFE 1 1 0 6 |KBSCAN:81|cnt0 (|KBSCAN:81|:16)
- 2 - B 10 AND2 4 0 0 2 |KBSCAN:81|:30
- 5 - B 10 AND2 4 0 0 6 |KBSCAN:81|:292
- 4 - B 10 AND2 4 0 0 6 |KBSCAN:81|:307
- 3 - B 10 AND2 4 0 0 6 |KBSCAN:81|:322
- 6 - B 10 AND2 4 0 0 9 |KBSCAN:81|:337
- 2 - B 01 OR2 0 2 0 4 |KBSCAN:81|:832
- 3 - B 02 OR2 0 2 0 3 |KBSCAN:81|:1087
- 5 - B 03 AND2 0 2 1 4 |KBSCAN:81|:1162
- 3 - B 03 AND2 0 2 1 4 |KBSCAN:81|:1170
- 1 - B 03 AND2 0 2 1 4 |KBSCAN:81|:1178
- 7 - B 03 OR2 0 2 1 0 |KBSCAN:81|:1181
- 7 - B 01 OR2 s 0 4 0 1 |KBSCAN:81|~1229~1
- 8 - B 01 OR2 0 4 0 1 |KBSCAN:81|:1235
- 4 - B 01 OR2 s 0 4 0 2 |KBSCAN:81|~1236~1
- 5 - B 01 OR2 0 3 1 0 |KBSCAN:81|:1241
- 6 - B 02 OR2 s 0 4 0 1 |KBSCAN:81|~1265~1
- 7 - B 02 OR2 s 0 4 0 1 |KBSCAN:81|~1265~2
- 1 - B 02 OR2 0 4 1 0 |KBSCAN:81|:1265
- 1 - B 10 OR2 ! 0 3 0 0 |KBSCAN:81|:1286
- 2 - B 02 OR2 s 0 2 0 1 |KBSCAN:81|~1289~1
- 4 - B 02 OR2 s 0 4 0 1 |KBSCAN:81|~1289~2
- 5 - B 02 OR2 s 0 4 0 1 |KBSCAN:81|~1289~3
- 8 - B 02 OR2 0 4 1 0 |KBSCAN:81|:1289
- 6 - B 01 OR2 s ! 0 3 0 1 |KBSCAN:81|~1313~1
- 1 - B 01 OR2 0 4 1 0 |KBSCAN:81|:1313
- 3 - B 01 AND2 0 3 1 0 |KBSCAN:81|:1325
- 6 - B 24 AND2 0 4 0 2 |mainctrl:45|lpm_add_sub:117|addcore:adder|:67
- 5 - B 24 OR2 0 4 0 2 |mainctrl:45|lpm_add_sub:117|addcore:adder|:77
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