📄 chengfa.rpt
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-- Node name is '|one_bit_adder:U_5_1|:15'
-- Equation name is '_LC3_B16', type is buried
_LC3_B16 = LCELL( _EQ081);
_EQ081 = A1 & B6 & _LC3_B15
# !A1 & _LC3_B14 & _LC3_B15
# A1 & _LC3_B14 & !_LC3_B15;
-- Node name is '|one_bit_adder:U_5_2|:8'
-- Equation name is '_LC8_B16', type is buried
_LC8_B16 = LCELL( _EQ082);
_EQ082 = A2 & B6 & _LC3_B16 & _LC8_B15
# !B6 & _LC3_B16 & !_LC8_B15
# !A2 & _LC3_B16 & !_LC8_B15
# !B6 & !_LC3_B16 & _LC8_B15
# !A2 & !_LC3_B16 & _LC8_B15
# A2 & B6 & !_LC3_B16 & !_LC8_B15;
-- Node name is '|one_bit_adder:U_5_2|:15'
-- Equation name is '_LC5_B16', type is buried
_LC5_B16 = LCELL( _EQ083);
_EQ083 = A2 & B6 & _LC3_B16
# !B6 & _LC3_B16 & _LC8_B15
# !A2 & _LC3_B16 & _LC8_B15
# A2 & B6 & _LC8_B15;
-- Node name is '|one_bit_adder:U_5_3|:8'
-- Equation name is '_LC1_B16', type is buried
_LC1_B16 = LCELL( _EQ084);
_EQ084 = A3 & B6 & _LC4_B15 & _LC5_B16
# !B6 & !_LC4_B15 & _LC5_B16
# !A3 & !_LC4_B15 & _LC5_B16
# !B6 & _LC4_B15 & !_LC5_B16
# !A3 & _LC4_B15 & !_LC5_B16
# A3 & B6 & !_LC4_B15 & !_LC5_B16;
-- Node name is '|one_bit_adder:U_5_3|:15'
-- Equation name is '_LC6_B16', type is buried
_LC6_B16 = LCELL( _EQ085);
_EQ085 = A3 & B6 & _LC5_B16
# !B6 & _LC4_B15 & _LC5_B16
# !A3 & _LC4_B15 & _LC5_B16
# A3 & B6 & _LC4_B15;
-- Node name is '|one_bit_adder:U_5_4|:8'
-- Equation name is '_LC7_B16', type is buried
_LC7_B16 = LCELL( _EQ086);
_EQ086 = A4 & B6 & _LC1_B15 & _LC6_B16
# !B6 & !_LC1_B15 & _LC6_B16
# !A4 & !_LC1_B15 & _LC6_B16
# !B6 & _LC1_B15 & !_LC6_B16
# !A4 & _LC1_B15 & !_LC6_B16
# A4 & B6 & !_LC1_B15 & !_LC6_B16;
-- Node name is '|one_bit_adder:U_5_4|:15'
-- Equation name is '_LC4_B16', type is buried
_LC4_B16 = LCELL( _EQ087);
_EQ087 = A4 & B6 & _LC6_B16
# !B6 & _LC1_B15 & _LC6_B16
# !A4 & _LC1_B15 & _LC6_B16
# A4 & B6 & _LC1_B15;
-- Node name is '|one_bit_adder:U_5_5|:8'
-- Equation name is '_LC1_B10', type is buried
_LC1_B10 = LCELL( _EQ088);
_EQ088 = A5 & B6 & _LC3_B10 & _LC4_B16
# !B6 & !_LC3_B10 & _LC4_B16
# !A5 & !_LC3_B10 & _LC4_B16
# !B6 & _LC3_B10 & !_LC4_B16
# !A5 & _LC3_B10 & !_LC4_B16
# A5 & B6 & !_LC3_B10 & !_LC4_B16;
-- Node name is '|one_bit_adder:U_5_5|:14'
-- Equation name is '_LC4_B10', type is buried
_LC4_B10 = LCELL( _EQ089);
_EQ089 = A5 & B6 & !_LC3_B10 & _LC4_B16
# !B6 & _LC3_B10 & _LC4_B16
# !A5 & _LC3_B10 & _LC4_B16;
-- Node name is '|one_bit_adder:U_5_5|~15~1'
-- Equation name is '_LC1_B3', type is buried
-- synthesized logic cell
_LC1_B3 = LCELL( _EQ090);
_EQ090 = B2 & B3 & _LC5_B9
# B3 & _LC8_B5;
-- Node name is '|one_bit_adder:U_5_5|~15~2'
-- Equation name is '_LC3_B3', type is buried
-- synthesized logic cell
_LC3_B3 = LCELL( _EQ091);
_EQ091 = B4 & B5 & _LC1_B3
# B4 & B5 & _LC2_B9;
-- Node name is '|one_bit_adder:U_5_5|~15~3'
-- Equation name is '_LC2_B3', type is buried
-- synthesized logic cell
_LC2_B3 = LCELL( _EQ092);
_EQ092 = _LC3_B3 & !_LC4_B3
# !B3 & _LC3_B3 & !_LC6_B15
# !_LC4_B3 & _LC6_B15;
-- Node name is '|one_bit_adder:U_5_5|~15~4'
-- Equation name is '_LC5_B3', type is buried
-- synthesized logic cell
_LC5_B3 = LCELL( _EQ093);
_EQ093 = !B1 & _LC5_B9
# _LC8_B5;
-- Node name is '|one_bit_adder:U_5_5|~15~5'
-- Equation name is '_LC6_B3', type is buried
-- synthesized logic cell
_LC6_B3 = LCELL( _EQ094);
_EQ094 = B2 & B4 & _LC5_B3;
-- Node name is '|one_bit_adder:U_5_5|~15~6'
-- Equation name is '_LC7_B3', type is buried
-- synthesized logic cell
_LC7_B3 = LCELL( _EQ095);
_EQ095 = B3 & !_LC2_B9 & _LC6_B3;
-- Node name is '|one_bit_adder:U_5_5|~15~7'
-- Equation name is '_LC8_B3', type is buried
-- synthesized logic cell
_LC8_B3 = LCELL( _EQ096);
_EQ096 = A6 & !B4 & !_LC1_B6
# _LC7_B3;
-- Node name is '|one_bit_adder:U_5_5|~15~8'
-- Equation name is '_LC7_B5', type is buried
-- synthesized logic cell
_LC7_B5 = LCELL( _EQ097);
_EQ097 = A6 & B3 & _LC5_B5
# A6 & B3 & _LC6_B5;
-- Node name is '|one_bit_adder:U_5_5|~15~9'
-- Equation name is '_LC3_B5', type is buried
-- synthesized logic cell
_LC3_B5 = LCELL( _EQ098);
_EQ098 = !_LC2_B9 & _LC7_B5
# _LC1_B6;
-- Node name is '|one_bit_adder:U_5_5|~15~10'
-- Equation name is '_LC5_B10', type is buried
-- synthesized logic cell
_LC5_B10 = LCELL( _EQ099);
_EQ099 = B4 & _LC3_B5 & !_LC6_B15
# !A6 & _LC3_B5;
-- Node name is '|one_bit_adder:U_5_5|~15~11'
-- Equation name is '_LC6_B10', type is buried
-- synthesized logic cell
_LC6_B10 = LCELL( _EQ100);
_EQ100 = B5 & !_LC6_B15 & _LC8_B3
# B5 & _LC5_B10;
-- Node name is '|one_bit_adder:U_5_5|~15~12'
-- Equation name is '_LC7_B10', type is buried
-- synthesized logic cell
_LC7_B10 = LCELL( _EQ101);
_EQ101 = A5 & B6 & _LC2_B3
# A5 & B6 & _LC6_B10;
-- Node name is '|one_bit_adder:U_5_6|:8'
-- Equation name is '_LC2_B10', type is buried
_LC2_B10 = LCELL( _EQ102);
_EQ102 = !A6 & _LC4_B10
# !A6 & _LC7_B10
# !B6 & _LC4_B10
# !B6 & _LC7_B10
# A6 & B6 & !_LC4_B10 & !_LC7_B10;
-- Node name is '|one_bit_adder:U_5_6|:14'
-- Equation name is '_LC8_B10', type is buried
_LC8_B10 = LCELL( _EQ103);
_EQ103 = A6 & B6 & _LC4_B10
# A6 & B6 & _LC7_B10;
-- Node name is ':3378'
-- Equation name is '_LC1_B4', type is buried
_LC1_B4 = LCELL( _EQ104);
_EQ104 = A0 & B0;
-- Node name is ':3463'
-- Equation name is '_LC4_B5', type is buried
!_LC4_B5 = _LC4_B5~NOT;
_LC4_B5~NOT = LCELL( _EQ105);
_EQ105 = !A5
# !B0;
-- Node name is ':3615'
-- Equation name is '_LC5_B13', type is buried
_LC5_B13 = LCELL( _EQ106);
_EQ106 = A1 & B1;
-- Node name is ':4456'
-- Equation name is '_LC4_B3', type is buried
!_LC4_B3 = _LC4_B3~NOT;
_LC4_B3~NOT = LCELL( _EQ107);
_EQ107 = !A6
# !B5;
-- Node name is ':4785'
-- Equation name is '_LC2_C12', type is buried
_LC2_C12 = LCELL( _EQ108);
_EQ108 = A7 & !B7
# !A7 & B7;
Project Information e:\mydds\verilog\chengfa.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:05
Memory Allocated
-----------------
Peak memory allocated during compilation = 26,501K
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