📄 chengfa.rpt
字号:
64 - - B -- OUTPUT 0 1 0 0 data_out10
38 - - - 10 OUTPUT 0 1 0 0 data_out11
37 - - - 09 OUTPUT 0 1 0 0 data_out12
25 - - B -- OUTPUT 0 1 0 0 data_out13
28 - - C -- OUTPUT 0 1 0 0 data_out14
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\mydds\verilog\chengfa.rpt
chengfa
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 4 - B 09 AND2 s 4 0 0 2 A5~1
- 4 - B 17 AND2 s 4 0 0 2 B0~1
- 8 - B 17 AND2 s 3 0 0 1 B0~2
- 5 - B 05 AND2 s 1 1 0 1 B6~1
- 6 - B 05 AND2 s 3 1 0 1 B6~2
- 6 - B 04 OR2 4 0 1 0 |one_bit_adder:U_0_0|:7
- 6 - B 13 AND2 4 0 0 2 |one_bit_adder:U_0_0|:12
- 7 - B 13 OR2 2 2 0 2 |one_bit_adder:U_0_1|:8
- 3 - B 13 OR2 2 2 0 3 |one_bit_adder:U_0_1|:15
- 2 - B 17 OR2 0 2 0 3 |one_bit_adder:U_0_2|:8
- 3 - B 17 OR2 4 0 0 3 |one_bit_adder:U_0_2|:13
- 1 - B 17 OR2 0 4 0 2 |one_bit_adder:U_0_3|:8
- 5 - B 17 OR2 4 0 0 2 |one_bit_adder:U_0_3|:13
- 7 - B 17 OR2 0 4 0 1 |one_bit_adder:U_0_3|:14
- 6 - B 17 OR2 1 2 0 3 |one_bit_adder:U_0_3|:15
- 7 - B 22 OR2 0 2 0 2 |one_bit_adder:U_0_4|:8
- 8 - B 04 OR2 4 0 0 3 |one_bit_adder:U_0_4|:13
- 7 - B 09 OR2 0 4 0 2 |one_bit_adder:U_0_5|:8
- 6 - B 09 OR2 4 0 0 2 |one_bit_adder:U_0_5|:13
- 5 - B 09 OR2 0 4 0 4 |one_bit_adder:U_0_5|:14
- 2 - B 05 OR2 2 2 0 3 |one_bit_adder:U_0_6|:8
- 8 - B 13 OR2 2 1 1 0 |one_bit_adder:U_1_0|:7
- 2 - B 13 AND2 2 1 0 2 |one_bit_adder:U_1_0|:12
- 1 - B 13 OR2 s 2 1 0 2 |one_bit_adder:U_1_1|~8~1
- 5 - B 22 OR2 2 2 0 2 |one_bit_adder:U_1_1|:15
- 3 - B 22 OR2 2 2 0 3 |one_bit_adder:U_1_2|:8
- 6 - B 22 OR2 2 2 0 2 |one_bit_adder:U_1_2|:15
- 2 - B 22 OR2 2 2 0 2 |one_bit_adder:U_1_3|:8
- 4 - B 22 OR2 2 2 0 2 |one_bit_adder:U_1_3|:15
- 5 - B 21 OR2 2 2 0 2 |one_bit_adder:U_1_4|:8
- 1 - B 22 OR2 2 2 0 2 |one_bit_adder:U_1_4|:15
- 1 - B 05 OR2 2 2 0 2 |one_bit_adder:U_1_5|:8
- 8 - B 09 AND2 2 1 0 1 |one_bit_adder:U_1_5|:12
- 8 - B 05 OR2 2 2 0 4 |one_bit_adder:U_1_5|:14
- 1 - B 09 OR2 2 2 0 3 |one_bit_adder:U_1_6|:8
- 4 - B 13 OR2 2 2 1 0 |one_bit_adder:U_2_0|:7
- 5 - B 24 OR2 2 2 0 2 |one_bit_adder:U_2_0|:12
- 6 - B 24 OR2 s 2 1 0 2 |one_bit_adder:U_2_1|~8~1
- 7 - B 24 OR2 2 2 0 2 |one_bit_adder:U_2_1|:15
- 1 - B 24 OR2 2 2 0 3 |one_bit_adder:U_2_2|:8
- 4 - B 24 OR2 2 2 0 2 |one_bit_adder:U_2_2|:15
- 1 - B 21 OR2 2 2 0 2 |one_bit_adder:U_2_3|:8
- 7 - B 21 OR2 2 2 0 2 |one_bit_adder:U_2_3|:15
- 8 - B 21 OR2 2 2 0 2 |one_bit_adder:U_2_4|:8
- 4 - B 21 OR2 2 2 0 2 |one_bit_adder:U_2_4|:15
- 3 - B 09 OR2 2 2 0 2 |one_bit_adder:U_2_5|:8
- 5 - B 06 AND2 2 1 0 1 |one_bit_adder:U_2_5|:12
- 2 - B 09 OR2 2 2 0 4 |one_bit_adder:U_2_5|:14
- 6 - B 06 OR2 2 2 0 3 |one_bit_adder:U_2_6|:8
- 8 - B 24 OR2 2 2 1 0 |one_bit_adder:U_3_0|:7
- 2 - B 24 OR2 2 2 0 2 |one_bit_adder:U_3_0|:12
- 3 - B 24 OR2 s 2 1 0 2 |one_bit_adder:U_3_1|~8~1
- 7 - B 14 OR2 2 2 0 2 |one_bit_adder:U_3_1|:15
- 8 - B 14 OR2 2 2 0 3 |one_bit_adder:U_3_2|:8
- 1 - B 14 OR2 2 2 0 2 |one_bit_adder:U_3_2|:15
- 3 - B 21 OR2 2 2 0 2 |one_bit_adder:U_3_3|:8
- 6 - B 21 OR2 2 2 0 2 |one_bit_adder:U_3_3|:15
- 2 - B 21 OR2 2 2 0 2 |one_bit_adder:U_3_4|:8
- 7 - B 06 OR2 2 2 0 2 |one_bit_adder:U_3_4|:15
- 4 - B 06 OR2 2 2 0 2 |one_bit_adder:U_3_5|:8
- 8 - B 06 AND2 2 1 0 1 |one_bit_adder:U_3_5|:12
- 1 - B 06 OR2 2 2 0 3 |one_bit_adder:U_3_5|:14
- 2 - B 06 OR2 2 2 0 3 |one_bit_adder:U_3_6|:8
- 2 - B 20 OR2 2 2 1 0 |one_bit_adder:U_4_0|:7
- 4 - B 14 OR2 2 2 0 2 |one_bit_adder:U_4_0|:12
- 6 - B 14 OR2 s 2 1 0 2 |one_bit_adder:U_4_1|~8~1
- 2 - B 14 OR2 2 2 0 2 |one_bit_adder:U_4_1|:15
- 3 - B 15 OR2 2 2 0 2 |one_bit_adder:U_4_2|:8
- 2 - B 15 OR2 2 2 0 2 |one_bit_adder:U_4_2|:15
- 8 - B 15 OR2 2 2 0 2 |one_bit_adder:U_4_3|:8
- 5 - B 15 OR2 2 2 0 2 |one_bit_adder:U_4_3|:15
- 4 - B 15 OR2 2 2 0 2 |one_bit_adder:U_4_4|:8
- 7 - B 15 OR2 2 2 0 2 |one_bit_adder:U_4_4|:15
- 1 - B 15 OR2 2 2 0 2 |one_bit_adder:U_4_5|:8
- 3 - B 06 AND2 2 1 0 1 |one_bit_adder:U_4_5|:12
- 6 - B 15 OR2 2 2 0 4 |one_bit_adder:U_4_5|:14
- 3 - B 10 OR2 2 2 0 2 |one_bit_adder:U_4_6|:8
- 5 - B 14 OR2 2 2 1 0 |one_bit_adder:U_5_0|:7
- 3 - B 14 OR2 2 2 0 2 |one_bit_adder:U_5_0|:12
- 2 - B 16 OR2 2 2 1 0 |one_bit_adder:U_5_1|:8
- 3 - B 16 OR2 2 2 0 2 |one_bit_adder:U_5_1|:15
- 8 - B 16 OR2 2 2 1 0 |one_bit_adder:U_5_2|:8
- 5 - B 16 OR2 2 2 0 2 |one_bit_adder:U_5_2|:15
- 1 - B 16 OR2 2 2 1 0 |one_bit_adder:U_5_3|:8
- 6 - B 16 OR2 2 2 0 2 |one_bit_adder:U_5_3|:15
- 7 - B 16 OR2 2 2 1 0 |one_bit_adder:U_5_4|:8
- 4 - B 16 OR2 2 2 0 2 |one_bit_adder:U_5_4|:15
- 1 - B 10 OR2 2 2 1 0 |one_bit_adder:U_5_5|:8
- 4 - B 10 OR2 2 2 0 2 |one_bit_adder:U_5_5|:14
- 1 - B 03 OR2 s 2 2 0 1 |one_bit_adder:U_5_5|~15~1
- 3 - B 03 OR2 s 2 2 0 1 |one_bit_adder:U_5_5|~15~2
- 2 - B 03 OR2 s 1 3 0 1 |one_bit_adder:U_5_5|~15~3
- 5 - B 03 OR2 s 1 2 0 1 |one_bit_adder:U_5_5|~15~4
- 6 - B 03 AND2 s 2 1 0 1 |one_bit_adder:U_5_5|~15~5
- 7 - B 03 AND2 s 1 2 0 1 |one_bit_adder:U_5_5|~15~6
- 8 - B 03 OR2 s 2 2 0 1 |one_bit_adder:U_5_5|~15~7
- 7 - B 05 OR2 s 2 2 0 1 |one_bit_adder:U_5_5|~15~8
- 3 - B 05 OR2 s 0 3 0 1 |one_bit_adder:U_5_5|~15~9
- 5 - B 10 OR2 s 2 2 0 1 |one_bit_adder:U_5_5|~15~10
- 6 - B 10 OR2 s 1 3 0 1 |one_bit_adder:U_5_5|~15~11
- 7 - B 10 OR2 s 2 2 0 2 |one_bit_adder:U_5_5|~15~12
- 2 - B 10 OR2 2 2 1 0 |one_bit_adder:U_5_6|:8
- 8 - B 10 OR2 2 2 1 0 |one_bit_adder:U_5_6|:14
- 1 - B 04 AND2 2 0 1 0 :3378
- 4 - B 05 OR2 ! 2 0 0 1 :3463
- 5 - B 13 AND2 2 0 0 2 :3615
- 4 - B 03 OR2 ! 2 0 0 1 :4456
- 2 - C 12 OR2 2 0 1 0 :4785
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: e:\mydds\verilog\chengfa.rpt
chengfa
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 1/ 48( 2%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
B: 26/ 96( 27%) 7/ 48( 14%) 23/ 48( 47%) 5/16( 31%) 4/16( 25%) 0/16( 0%)
C: 2/ 96( 2%) 1/ 48( 2%) 0/ 48( 0%) 2/16( 12%) 1/16( 6%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
04: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
10: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
14: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
15: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
16: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
20: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
24: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\mydds\verilog\chengfa.rpt
chengfa
** EQUATIONS **
A0 : INPUT;
A1 : INPUT;
A2 : INPUT;
A3 : INPUT;
A4 : INPUT;
A5 : INPUT;
A6 : INPUT;
A7 : INPUT;
B0 : INPUT;
B1 : INPUT;
B2 : INPUT;
B3 : INPUT;
B4 : INPUT;
B5 : INPUT;
B6 : INPUT;
B7 : INPUT;
-- Node name is 'A5~1'
-- Equation name is 'A5~1', location is LC4_B9, type is buried.
-- synthesized logic cell
_LC4_B9 = LCELL( _EQ001);
_EQ001 = A4 & A5 & B0 & B1;
-- Node name is 'B0~1'
-- Equation name is 'B0~1', location is LC4_B17, type is buried.
-- synthesized logic cell
_LC4_B17 = LCELL( _EQ002);
_EQ002 = A2 & A3 & B0 & B1;
-- Node name is 'B0~2'
-- Equation name is 'B0~2', location is LC8_B17, type is buried.
-- synthesized logic cell
_LC8_B17 = LCELL( _EQ003);
_EQ003 = A4 & B0 & B1;
-- Node name is 'B6~1'
-- Equation name is 'B6~1', location is LC5_B5, type is buried.
-- synthesized logic cell
_LC5_B5 = LCELL( _EQ004);
_EQ004 = !B2 & !_LC8_B5;
-- Node name is 'B6~2'
-- Equation name is 'B6~2', location is LC6_B5, type is buried.
-- synthesized logic cell
_LC6_B5 = LCELL( _EQ005);
_EQ005 = !B0 & B1 & B2 & !_LC5_B9;
-- Node name is 'data_out0'
-- Equation name is 'data_out0', type is output
data_out0 = _LC1_B4;
-- Node name is 'data_out1'
-- Equation name is 'data_out1', type is output
data_out1 = _LC6_B4;
-- Node name is 'data_out2'
-- Equation name is 'data_out2', type is output
data_out2 = _LC8_B13;
-- Node name is 'data_out3'
-- Equation name is 'data_out3', type is output
data_out3 = _LC4_B13;
-- Node name is 'data_out4'
-- Equation name is 'data_out4', type is output
data_out4 = _LC8_B24;
-- Node name is 'data_out5'
-- Equation name is 'data_out5', type is output
data_out5 = _LC2_B20;
-- Node name is 'data_out6'
-- Equation name is 'data_out6', type is output
data_out6 = _LC5_B14;
-- Node name is 'data_out7'
-- Equation name is 'data_out7', type is output
data_out7 = _LC2_B16;
-- Node name is 'data_out8'
-- Equation name is 'data_out8', type is output
data_out8 = _LC8_B16;
-- Node name is 'data_out9'
-- Equation name is 'data_out9', type is output
data_out9 = _LC1_B16;
-- Node name is 'data_out10'
-- Equation name is 'data_out10', type is output
data_out10 = _LC7_B16;
-- Node name is 'data_out11'
-- Equation name is 'data_out11', type is output
data_out11 = _LC1_B10;
-- Node name is 'data_out12'
-- Equation name is 'data_out12', type is output
data_out12 = _LC2_B10;
-- Node name is 'data_out13'
-- Equation name is 'data_out13', type is output
data_out13 = _LC8_B10;
-- Node name is 'data_out14'
-- Equation name is 'data_out14', type is output
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