tiao.rpt

DDS-320-func： 在采用 320x240 屏的设计实验箱上运行

-- Node name is ':65' = 'counter14' 
-- Equation name is 'counter14', location is LC4_A22, type is buried.
counter14 = DFFE( _EQ014,  fc,  VCC,  VCC,  VCC);
  _EQ014 = !counter13 &  counter14
         #  counter14 & !_LC7_A22
         #  counter13 & !counter14 &  _LC7_A22;

-- Node name is ':64' = 'counter15' 
-- Equation name is 'counter15', location is LC6_A22, type is buried.
counter15 = DFFE( _EQ015,  fc,  VCC,  VCC,  VCC);
  _EQ015 = !counter13 &  counter15
         #  counter15 & !_LC7_A22
         # !counter14 &  counter15
         #  counter13 &  counter14 & !counter15 &  _LC7_A22;

-- Node name is ':39' = 'devider0' 
-- Equation name is 'devider0', location is LC3_A1, type is buried.
devider0 = DFFE( _EQ016, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ016 = !devider0 & !devider1
         # !devider0 &  _LC4_A1;

-- Node name is ':38' = 'devider1' 
-- Equation name is 'devider1', location is LC1_A1, type is buried.
devider1 = DFFE( _EQ017, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ017 =  devider0 & !devider1
         # !devider0 &  devider1 &  _LC4_A1;

-- Node name is ':37' = 'devider2' 
-- Equation name is 'devider2', location is LC8_A1, type is buried.
devider2 = DFFE( _EQ018, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ018 = !devider0 &  devider2 & !_LC2_A1
         # !devider1 &  devider2 & !_LC2_A1
         #  devider0 &  devider1 & !devider2 & !_LC2_A1;

-- Node name is ':36' = 'devider3' 
-- Equation name is 'devider3', location is LC7_A1, type is buried.
devider3 = DFFE( _EQ019, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ019 = !devider2 &  devider3 & !_LC2_A1
         #  devider3 & !_LC1_A8 & !_LC2_A1
         #  devider2 & !devider3 &  _LC1_A8 & !_LC2_A1;

-- Node name is ':35' = 'devider4' 
-- Equation name is 'devider4', location is LC6_A1, type is buried.
devider4 = DFFE( _EQ020, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ020 = !devider3 &  devider4 & !_LC2_A1
         #  devider4 & !_LC2_A1 & !_LC5_A1
         #  devider3 & !devider4 & !_LC2_A1 &  _LC5_A1;

-- Node name is ':46' = 'fc' 
-- Equation name is 'fc', location is LC7_A18, type is buried.
fc       = DFFE(!fc, GLOBAL( clk),  VCC,  VCC,  _LC2_A1);

-- Node name is 'phase0' 
-- Equation name is 'phase0', type is output 
phase0   =  counter8;

-- Node name is 'phase1' 
-- Equation name is 'phase1', type is output 
phase1   =  counter9;

-- Node name is 'phase2' 
-- Equation name is 'phase2', type is output 
phase2   =  counter10;

-- Node name is 'phase3' 
-- Equation name is 'phase3', type is output 
phase3   =  counter11;

-- Node name is 'phase4' 
-- Equation name is 'phase4', type is output 
phase4   =  counter12;

-- Node name is 'phase5' 
-- Equation name is 'phase5', type is output 
phase5   =  counter13;

-- Node name is 'phase6' 
-- Equation name is 'phase6', type is output 
phase6   =  counter14;

-- Node name is 'phase7' 
-- Equation name is 'phase7', type is output 
phase7   =  counter15;

-- Node name is '|lpm_add_sub:88|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC1_A8', type is buried 
_LC1_A8  = LCELL( _EQ021);
  _EQ021 =  devider0 &  devider1;

-- Node name is '|lpm_add_sub:88|addcore:adder|:63' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_A1', type is buried 
_LC5_A1  = LCELL( _EQ022);
  _EQ022 =  devider0 &  devider1 &  devider2;

-- Node name is '|lpm_add_sub:89|addcore:adder|pcarry3' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC1_A13', type is buried 
_LC1_A13 = LCELL( _EQ023);
  _EQ023 =  counter0
         #  counter1
         #  counter2
         #  counter3;

-- Node name is '|lpm_add_sub:89|addcore:adder|pcarry6' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC4_A21', type is buried 
_LC4_A21 = LCELL( _EQ024);
  _EQ024 =  counter4
         #  _LC1_A13
         #  counter5
         #  counter6;

-- Node name is '|lpm_add_sub:89|addcore:adder|pcarry9' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC6_A21', type is buried 
_LC6_A21 = LCELL( _EQ025);
  _EQ025 =  counter7
         #  _LC4_A21
         #  counter8
         #  counter9;

-- Node name is '|lpm_add_sub:89|addcore:adder|:147' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC7_A22', type is buried 
_LC7_A22 = LCELL( _EQ026);
  _EQ026 =  counter10 &  counter11 &  counter12
         #  counter11 &  counter12 &  _LC6_A21;

-- Node name is '~11~1' 
-- Equation name is '~11~1', location is LC4_A1, type is buried.
-- synthesized logic cell 
!_LC4_A1 = _LC4_A1~NOT;
_LC4_A1~NOT = LCELL( _EQ027);
  _EQ027 =  devider2 & !devider3 & !devider4;

-- Node name is ':11' 
-- Equation name is '_LC2_A1', type is buried 
_LC2_A1  = LCELL( _EQ028);
  _EQ028 = !devider0 &  devider1 & !_LC4_A1;



Project Information                                  e:\mydds\verilog\tiao.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:03


Memory Allocated
-----------------

Peak memory allocated during compilation  = 19,853K