📄 tiao.rpt
字号:
tiao
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
69 - - A -- OUTPUT 0 1 0 0 phase0
16 - - A -- OUTPUT 0 1 0 0 phase1
73 - - A -- OUTPUT 0 1 0 0 phase2
70 - - A -- OUTPUT 0 1 0 0 phase3
17 - - A -- OUTPUT 0 1 0 0 phase4
71 - - A -- OUTPUT 0 1 0 0 phase5
81 - - - 22 OUTPUT 0 1 0 0 phase6
19 - - A -- OUTPUT 0 1 0 0 phase7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\mydds\verilog\tiao.rpt
tiao
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - A 08 AND2 0 2 0 1 |lpm_add_sub:88|addcore:adder|:59
- 5 - A 01 AND2 0 3 0 1 |lpm_add_sub:88|addcore:adder|:63
- 1 - A 13 OR2 0 4 0 4 |lpm_add_sub:89|addcore:adder|pcarry3
- 4 - A 21 OR2 0 4 0 4 |lpm_add_sub:89|addcore:adder|pcarry6
- 6 - A 21 OR2 0 4 0 4 |lpm_add_sub:89|addcore:adder|pcarry9
- 7 - A 22 OR2 0 4 0 3 |lpm_add_sub:89|addcore:adder|:147
- 4 - A 01 AND2 s ! 0 3 0 3 ~11~1
- 2 - A 01 AND2 0 3 0 4 :11
- 6 - A 01 DFFE + 0 3 0 1 devider4 (:35)
- 7 - A 01 DFFE + 0 3 0 2 devider3 (:36)
- 8 - A 01 DFFE + 0 3 0 3 devider2 (:37)
- 1 - A 01 DFFE + 0 2 0 5 devider1 (:38)
- 3 - A 01 DFFE + 0 2 0 5 devider0 (:39)
- 7 - A 18 DFFE + 0 1 0 16 fc (:46)
- 6 - A 22 DFFE 0 4 1 0 counter15 (:64)
- 4 - A 22 DFFE 0 3 1 1 counter14 (:65)
- 3 - A 22 DFFE 0 2 1 2 counter13 (:66)
- 2 - A 22 DFFE 0 4 1 1 counter12 (:67)
- 5 - A 22 DFFE 0 3 1 2 counter11 (:68)
- 1 - A 22 DFFE 0 2 1 3 counter10 (:69)
- 1 - A 21 DFFE 0 4 1 1 counter9 (:70)
- 8 - A 21 DFFE 0 3 1 2 counter8 (:71)
- 5 - A 21 DFFE 0 2 0 3 counter7 (:72)
- 3 - A 21 DFFE 0 4 0 1 counter6 (:73)
- 2 - A 21 DFFE 0 3 0 2 counter5 (:74)
- 2 - A 13 DFFE 0 2 0 3 counter4 (:75)
- 6 - A 13 DFFE 0 4 0 1 counter3 (:76)
- 5 - A 13 DFFE 0 3 0 2 counter2 (:77)
- 4 - A 13 DFFE 0 2 0 3 counter1 (:78)
- 3 - A 13 DFFE 0 1 0 4 counter0 (:79)
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: e:\mydds\verilog\tiao.rpt
tiao
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 5/ 96( 5%) 3/ 48( 6%) 8/ 48( 16%) 0/16( 0%) 7/16( 43%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\mydds\verilog\tiao.rpt
tiao
** CLOCK SIGNALS **
Type Fan-out Name
DFF 17 fc
INPUT 6 clk
Device-Specific Information: e:\mydds\verilog\tiao.rpt
tiao
** EQUATIONS **
clk : INPUT;
-- Node name is ':79' = 'counter0'
-- Equation name is 'counter0', location is LC3_A13, type is buried.
counter0 = DFFE(!counter0, fc, VCC, VCC, VCC);
-- Node name is ':78' = 'counter1'
-- Equation name is 'counter1', location is LC4_A13, type is buried.
counter1 = DFFE( _EQ001, fc, VCC, VCC, VCC);
_EQ001 = counter0 & counter1
# !counter0 & !counter1;
-- Node name is ':77' = 'counter2'
-- Equation name is 'counter2', location is LC5_A13, type is buried.
counter2 = DFFE( _EQ002, fc, VCC, VCC, VCC);
_EQ002 = counter0 & counter2
# counter1 & counter2
# !counter0 & !counter1 & !counter2;
-- Node name is ':76' = 'counter3'
-- Equation name is 'counter3', location is LC6_A13, type is buried.
counter3 = DFFE( _EQ003, fc, VCC, VCC, VCC);
_EQ003 = counter0 & counter3
# counter1 & counter3
# counter2 & counter3
# !counter0 & !counter1 & !counter2 & !counter3;
-- Node name is ':75' = 'counter4'
-- Equation name is 'counter4', location is LC2_A13, type is buried.
counter4 = DFFE( _EQ004, fc, VCC, VCC, VCC);
_EQ004 = counter4 & _LC1_A13
# !counter4 & !_LC1_A13;
-- Node name is ':74' = 'counter5'
-- Equation name is 'counter5', location is LC2_A21, type is buried.
counter5 = DFFE( _EQ005, fc, VCC, VCC, VCC);
_EQ005 = counter4 & counter5
# counter5 & _LC1_A13
# !counter4 & !counter5 & !_LC1_A13;
-- Node name is ':73' = 'counter6'
-- Equation name is 'counter6', location is LC3_A21, type is buried.
counter6 = DFFE( _EQ006, fc, VCC, VCC, VCC);
_EQ006 = counter4 & counter6
# counter6 & _LC1_A13
# counter5 & counter6
# !counter4 & !counter5 & !counter6 & !_LC1_A13;
-- Node name is ':72' = 'counter7'
-- Equation name is 'counter7', location is LC5_A21, type is buried.
counter7 = DFFE( _EQ007, fc, VCC, VCC, VCC);
_EQ007 = counter7 & _LC4_A21
# !counter7 & !_LC4_A21;
-- Node name is ':71' = 'counter8'
-- Equation name is 'counter8', location is LC8_A21, type is buried.
counter8 = DFFE( _EQ008, fc, VCC, VCC, VCC);
_EQ008 = counter7 & counter8
# counter8 & _LC4_A21
# !counter7 & !counter8 & !_LC4_A21;
-- Node name is ':70' = 'counter9'
-- Equation name is 'counter9', location is LC1_A21, type is buried.
counter9 = DFFE( _EQ009, fc, VCC, VCC, VCC);
_EQ009 = counter7 & counter9
# counter9 & _LC4_A21
# counter8 & counter9
# !counter7 & !counter8 & !counter9 & !_LC4_A21;
-- Node name is ':69' = 'counter10'
-- Equation name is 'counter10', location is LC1_A22, type is buried.
counter10 = DFFE( _EQ010, fc, VCC, VCC, VCC);
_EQ010 = counter10 & _LC6_A21
# !counter10 & !_LC6_A21;
-- Node name is ':68' = 'counter11'
-- Equation name is 'counter11', location is LC5_A22, type is buried.
counter11 = DFFE( _EQ011, fc, VCC, VCC, VCC);
_EQ011 = !counter10 & counter11 & !_LC6_A21
# counter10 & !counter11
# !counter11 & _LC6_A21;
-- Node name is ':67' = 'counter12'
-- Equation name is 'counter12', location is LC2_A22, type is buried.
counter12 = DFFE( _EQ012, fc, VCC, VCC, VCC);
_EQ012 = !counter10 & counter12 & !_LC6_A21
# !counter11 & counter12
# counter10 & counter11 & !counter12
# counter11 & !counter12 & _LC6_A21;
-- Node name is ':66' = 'counter13'
-- Equation name is 'counter13', location is LC3_A22, type is buried.
counter13 = DFFE( _EQ013, fc, VCC, VCC, VCC);
_EQ013 = counter13 & !_LC7_A22
# !counter13 & _LC7_A22;
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