📄 chengfa2.rpt
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-- Node name is '|one_bit_adder:U_4_4|:8'
-- Equation name is '_LC6_C15', type is buried
_LC6_C15 = LCELL( _EQ078);
_EQ078 = A4 & B5 & _LC2_C2 & _LC3_C14
# !B5 & !_LC2_C2 & _LC3_C14
# !A4 & !_LC2_C2 & _LC3_C14
# !B5 & _LC2_C2 & !_LC3_C14
# !A4 & _LC2_C2 & !_LC3_C14
# A4 & B5 & !_LC2_C2 & !_LC3_C14;
-- Node name is '|one_bit_adder:U_4_4|:15'
-- Equation name is '_LC7_C15', type is buried
_LC7_C15 = LCELL( _EQ079);
_EQ079 = A4 & B5 & _LC3_C14
# !B5 & _LC2_C2 & _LC3_C14
# !A4 & _LC2_C2 & _LC3_C14
# A4 & B5 & _LC2_C2;
-- Node name is '|one_bit_adder:U_4_5|:8'
-- Equation name is '_LC1_C20', type is buried
_LC1_C20 = LCELL( _EQ080);
_EQ080 = A5 & B5 & _LC7_C15 & _LC8_C2
# !A5 & _LC7_C15 & !_LC8_C2
# !B5 & _LC7_C15 & !_LC8_C2
# !A5 & !_LC7_C15 & _LC8_C2
# !B5 & !_LC7_C15 & _LC8_C2
# A5 & B5 & !_LC7_C15 & !_LC8_C2;
-- Node name is '|one_bit_adder:U_4_5|:15'
-- Equation name is '_LC3_C20', type is buried
_LC3_C20 = LCELL( _EQ081);
_EQ081 = A5 & B5 & _LC7_C15
# !A5 & _LC7_C15 & _LC8_C2
# !B5 & _LC7_C15 & _LC8_C2
# A5 & B5 & _LC8_C2;
-- Node name is '|one_bit_adder:U_4_6|:8'
-- Equation name is '_LC4_C20', type is buried
_LC4_C20 = LCELL( _EQ082);
_EQ082 = A6 & B5 & _LC3_C20 & _LC5_C2
# !A6 & _LC3_C20 & !_LC5_C2
# !B5 & _LC3_C20 & !_LC5_C2
# !A6 & !_LC3_C20 & _LC5_C2
# !B5 & !_LC3_C20 & _LC5_C2
# A6 & B5 & !_LC3_C20 & !_LC5_C2;
-- Node name is '|one_bit_adder:U_4_6|:15'
-- Equation name is '_LC7_C20', type is buried
_LC7_C20 = LCELL( _EQ083);
_EQ083 = A6 & B5 & _LC3_C20
# !A6 & _LC3_C20 & _LC5_C2
# !B5 & _LC3_C20 & _LC5_C2
# A6 & B5 & _LC5_C2;
-- Node name is '|one_bit_adder:U_5_0|:7'
-- Equation name is '_LC3_C22', type is buried
_LC3_C22 = LCELL( _EQ084);
_EQ084 = !B6 & !_LC5_C22 & _LC8_C8
# !B6 & _LC5_C22 & !_LC8_C8
# !A0 & !_LC5_C22 & _LC8_C8
# !A0 & _LC5_C22 & !_LC8_C8
# A0 & B6 & _LC5_C22 & _LC8_C8
# A0 & B6 & !_LC5_C22 & !_LC8_C8;
-- Node name is '|one_bit_adder:U_5_0|:12'
-- Equation name is '_LC6_C22', type is buried
_LC6_C22 = LCELL( _EQ085);
_EQ085 = A0 & B6 & !_LC5_C22 & _LC8_C8
# A0 & B6 & _LC5_C22 & !_LC8_C8;
-- Node name is '|one_bit_adder:U_5_1|:8'
-- Equation name is '_LC2_C22', type is buried
_LC2_C22 = LCELL( _EQ086);
_EQ086 = A1 & B6 & _LC6_C22 & _LC8_C22
# !B6 & !_LC6_C22 & _LC8_C22
# !A1 & !_LC6_C22 & _LC8_C22
# !B6 & _LC6_C22 & !_LC8_C22
# !A1 & _LC6_C22 & !_LC8_C22
# A1 & B6 & !_LC6_C22 & !_LC8_C22;
-- Node name is '|one_bit_adder:U_5_1|:15'
-- Equation name is '_LC4_C22', type is buried
_LC4_C22 = LCELL( _EQ087);
_EQ087 = A1 & B6 & _LC8_C22
# !A1 & _LC6_C22 & _LC8_C22
# A1 & _LC6_C22 & !_LC8_C22;
-- Node name is '|one_bit_adder:U_5_2|:8'
-- Equation name is '_LC4_C15', type is buried
_LC4_C15 = LCELL( _EQ088);
_EQ088 = _LC4_C22 & !_LC5_C14
# !_LC4_C22 & _LC5_C14;
-- Node name is '|one_bit_adder:U_5_2|:13'
-- Equation name is '_LC5_C14', type is buried
_LC5_C14 = LCELL( _EQ089);
_EQ089 = !B6 & _LC1_C22 & !_LC7_C14
# !B6 & !_LC1_C22 & _LC7_C14
# !A2 & _LC1_C22 & !_LC7_C14
# !A2 & !_LC1_C22 & _LC7_C14
# A2 & B6 & _LC1_C22 & _LC7_C14
# A2 & B6 & !_LC1_C22 & !_LC7_C14;
-- Node name is '|one_bit_adder:U_5_2|:15'
-- Equation name is '_LC5_C15', type is buried
_LC5_C15 = LCELL( _EQ090);
_EQ090 = _LC4_C22 & _LC5_C14
# _LC4_C14;
-- Node name is '|one_bit_adder:U_5_3|:8'
-- Equation name is '_LC1_C15', type is buried
_LC1_C15 = LCELL( _EQ091);
_EQ091 = A3 & B6 & _LC5_C15 & _LC6_C15
# !B6 & _LC5_C15 & !_LC6_C15
# !A3 & _LC5_C15 & !_LC6_C15
# !B6 & !_LC5_C15 & _LC6_C15
# !A3 & !_LC5_C15 & _LC6_C15
# A3 & B6 & !_LC5_C15 & !_LC6_C15;
-- Node name is '|one_bit_adder:U_5_3|:15'
-- Equation name is '_LC8_C15', type is buried
_LC8_C15 = LCELL( _EQ092);
_EQ092 = A3 & B6 & _LC5_C15
# !B6 & _LC5_C15 & _LC6_C15
# !A3 & _LC5_C15 & _LC6_C15
# A3 & B6 & _LC6_C15;
-- Node name is '|one_bit_adder:U_5_4|:8'
-- Equation name is '_LC2_C15', type is buried
_LC2_C15 = LCELL( _EQ093);
_EQ093 = A4 & B6 & _LC1_C20 & _LC8_C15
# !B6 & !_LC1_C20 & _LC8_C15
# !A4 & !_LC1_C20 & _LC8_C15
# !B6 & _LC1_C20 & !_LC8_C15
# !A4 & _LC1_C20 & !_LC8_C15
# A4 & B6 & !_LC1_C20 & !_LC8_C15;
-- Node name is '|one_bit_adder:U_5_4|:15'
-- Equation name is '_LC3_C15', type is buried
_LC3_C15 = LCELL( _EQ094);
_EQ094 = A4 & B6 & _LC8_C15
# !B6 & _LC1_C20 & _LC8_C15
# !A4 & _LC1_C20 & _LC8_C15
# A4 & B6 & _LC1_C20;
-- Node name is '|one_bit_adder:U_5_5|:8'
-- Equation name is '_LC8_C20', type is buried
_LC8_C20 = LCELL( _EQ095);
_EQ095 = A5 & B6 & _LC3_C15 & _LC4_C20
# !B6 & _LC3_C15 & !_LC4_C20
# !A5 & _LC3_C15 & !_LC4_C20
# !B6 & !_LC3_C15 & _LC4_C20
# !A5 & !_LC3_C15 & _LC4_C20
# A5 & B6 & !_LC3_C15 & !_LC4_C20;
-- Node name is '|one_bit_adder:U_5_5|:15'
-- Equation name is '_LC5_C20', type is buried
_LC5_C20 = LCELL( _EQ096);
_EQ096 = A5 & B6 & _LC3_C15
# !B6 & _LC3_C15 & _LC4_C20
# !A5 & _LC3_C15 & _LC4_C20
# A5 & B6 & _LC4_C20;
-- Node name is '|one_bit_adder:U_5_6|:8'
-- Equation name is '_LC2_C20', type is buried
_LC2_C20 = LCELL( _EQ097);
_EQ097 = A6 & B6 & _LC5_C20 & _LC7_C20
# !A6 & _LC5_C20 & !_LC7_C20
# !B6 & _LC5_C20 & !_LC7_C20
# !A6 & !_LC5_C20 & _LC7_C20
# !B6 & !_LC5_C20 & _LC7_C20
# A6 & B6 & !_LC5_C20 & !_LC7_C20;
-- Node name is '|one_bit_adder:U_5_6|:15'
-- Equation name is '_LC6_C20', type is buried
_LC6_C20 = LCELL( _EQ098);
_EQ098 = A6 & B6 & _LC5_C20
# !A6 & _LC5_C20 & _LC7_C20
# !B6 & _LC5_C20 & _LC7_C20
# A6 & B6 & _LC7_C20;
-- Node name is ':5144'
-- Equation name is '_LC1_C11', type is buried
_LC1_C11 = LCELL( _EQ099);
_EQ099 = A0 & B0;
-- Node name is ':5182'
-- Equation name is '_LC3_C11', type is buried
_LC3_C11 = LCELL( _EQ100);
_EQ100 = A2 & B0;
-- Node name is ':5201'
-- Equation name is '_LC5_C3', type is buried
_LC5_C3 = LCELL( _EQ101);
_EQ101 = A3 & B0;
-- Node name is ':5239'
-- Equation name is '_LC6_C10', type is buried
_LC6_C10 = LCELL( _EQ102);
_EQ102 = A5 & B0;
-- Node name is ':5487'
-- Equation name is '_LC4_C10', type is buried
_LC4_C10 = LCELL( _EQ103);
_EQ103 = A4 & B1;
Project Information e:\mydds\verilog\chengfa2.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:02
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:01
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:06
Memory Allocated
-----------------
Peak memory allocated during compilation = 26,710K
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