📄 chengfa2.rpt
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Device-Specific Information: e:\mydds\verilog\chengfa2.rpt
chengfa2
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
27 - - C -- OUTPUT 0 1 0 0 data_out0
39 - - - 11 OUTPUT 0 1 0 0 data_out1
3 - - - 12 OUTPUT 0 1 0 0 data_out2
11 - - - 01 OUTPUT 0 1 0 0 data_out3
28 - - C -- OUTPUT 0 1 0 0 data_out4
5 - - - 05 OUTPUT 0 1 0 0 data_out5
81 - - - 22 OUTPUT 0 1 0 0 data_out6
54 - - - 21 OUTPUT 0 1 0 0 data_out7
60 - - C -- OUTPUT 0 1 0 0 data_out8
48 - - - 15 OUTPUT 0 1 0 0 data_out9
49 - - - 16 OUTPUT 0 1 0 0 data_out10
70 - - A -- OUTPUT 0 1 0 0 data_out11
53 - - - 20 OUTPUT 0 1 0 0 data_out12
52 - - - 19 OUTPUT 0 1 0 0 data_out13
17 - - A -- OUTPUT 0 0 0 0 data_out14
23 - - B -- OUTPUT 0 1 0 0 data_out15
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\mydds\verilog\chengfa2.rpt
chengfa2
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 6 - C 03 AND2 s 2 1 0 2 B0~1
- 8 - C 03 AND2 s 0 2 0 1 B0~2
- 2 - C 07 OR2 s 2 2 0 1 B3~1
- 6 - C 06 OR2 s 2 2 0 1 B4~1
- 8 - C 14 OR2 s 2 2 0 1 B5~1
- 4 - C 14 OR2 s 2 2 0 1 B6~1
- 4 - B 07 LCELL s 1 0 1 0 data_out15~1
- 5 - C 11 OR2 4 0 1 0 |one_bit_adder:U_0_0|:7
- 4 - C 11 AND2 4 0 0 4 |one_bit_adder:U_0_0|:12
- 2 - C 11 OR2 s 2 1 0 2 |one_bit_adder:U_0_1|~8~1
- 7 - C 01 AND2 2 1 0 2 |one_bit_adder:U_0_1|:12
- 8 - C 01 OR2 1 3 0 3 |one_bit_adder:U_0_2|:8
- 4 - C 03 OR2 2 1 0 4 |one_bit_adder:U_0_2|:13
- 1 - C 01 OR2 1 3 0 2 |one_bit_adder:U_0_2|:14
- 2 - C 03 OR2 0 3 0 2 |one_bit_adder:U_0_3|:8
- 7 - C 03 OR2 4 0 0 3 |one_bit_adder:U_0_3|:13
- 1 - C 03 OR2 0 4 0 3 |one_bit_adder:U_0_3|:15
- 3 - C 10 OR2 0 3 0 2 |one_bit_adder:U_0_4|:8
- 2 - C 10 OR2 0 4 0 2 |one_bit_adder:U_0_5|:8
- 7 - C 10 OR2 4 0 0 3 |one_bit_adder:U_0_5|:13
- 5 - C 10 OR2 0 4 0 2 |one_bit_adder:U_0_5|:14
- 8 - C 07 OR2 2 2 0 1 |one_bit_adder:U_0_5|:15
- 7 - C 07 OR2 2 2 0 2 |one_bit_adder:U_0_6|:8
- 6 - C 11 OR2 2 2 1 0 |one_bit_adder:U_1_0|:7
- 3 - C 01 OR2 2 2 0 2 |one_bit_adder:U_1_0|:12
- 5 - C 01 OR2 s 2 1 0 2 |one_bit_adder:U_1_1|~8~1
- 6 - C 01 OR2 2 2 0 2 |one_bit_adder:U_1_1|:15
- 5 - C 05 OR2 2 2 0 3 |one_bit_adder:U_1_2|:8
- 6 - C 05 OR2 2 2 0 2 |one_bit_adder:U_1_2|:15
- 7 - C 05 OR2 2 2 0 2 |one_bit_adder:U_1_3|:8
- 1 - C 05 OR2 2 2 0 2 |one_bit_adder:U_1_3|:15
- 5 - C 06 OR2 2 2 0 2 |one_bit_adder:U_1_4|:8
- 6 - C 07 OR2 2 2 0 2 |one_bit_adder:U_1_4|:15
- 1 - C 07 OR2 2 2 0 2 |one_bit_adder:U_1_5|:8
- 4 - C 07 OR2 2 2 0 3 |one_bit_adder:U_1_5|:15
- 3 - C 07 OR2 3 1 0 3 |one_bit_adder:U_1_6|:13
- 1 - C 02 AND2 s 3 0 0 1 |one_bit_adder:U_1_6|~15~1
- 8 - C 11 OR2 s 2 2 0 1 |one_bit_adder:U_1_6|~15~2
- 7 - C 11 OR2 s 1 3 0 1 |one_bit_adder:U_1_6|~15~3
- 3 - C 03 OR2 s 1 3 0 1 |one_bit_adder:U_1_6|~15~4
- 1 - C 10 OR2 s 0 4 0 1 |one_bit_adder:U_1_6|~15~5
- 3 - C 02 OR2 0 4 0 2 |one_bit_adder:U_1_6|:15
- 2 - C 01 OR2 2 2 1 0 |one_bit_adder:U_2_0|:7
- 4 - C 01 OR2 2 2 0 2 |one_bit_adder:U_2_0|:12
- 1 - C 08 OR2 s 2 1 0 2 |one_bit_adder:U_2_1|~8~1
- 4 - C 08 OR2 2 2 0 2 |one_bit_adder:U_2_1|:15
- 8 - C 05 OR2 2 2 0 3 |one_bit_adder:U_2_2|:8
- 2 - C 05 OR2 2 2 0 2 |one_bit_adder:U_2_2|:15
- 1 - C 06 OR2 2 2 0 2 |one_bit_adder:U_2_3|:8
- 7 - C 06 OR2 2 2 0 2 |one_bit_adder:U_2_3|:15
- 3 - C 06 OR2 2 2 0 2 |one_bit_adder:U_2_4|:8
- 8 - C 06 OR2 2 2 0 3 |one_bit_adder:U_2_4|:15
- 5 - C 07 OR2 2 2 0 3 |one_bit_adder:U_2_5|:13
- 4 - C 06 OR2 0 3 0 2 |one_bit_adder:U_2_5|:15
- 4 - C 02 OR2 2 2 0 2 |one_bit_adder:U_2_6|:8
- 7 - C 02 OR2 2 2 0 2 |one_bit_adder:U_2_6|:15
- 2 - C 08 OR2 2 2 1 0 |one_bit_adder:U_3_0|:7
- 3 - C 08 OR2 2 2 0 2 |one_bit_adder:U_3_0|:12
- 6 - C 08 OR2 s 2 1 0 2 |one_bit_adder:U_3_1|~8~1
- 7 - C 08 OR2 2 2 0 2 |one_bit_adder:U_3_1|:15
- 8 - C 08 OR2 2 2 0 3 |one_bit_adder:U_3_2|:8
- 5 - C 08 OR2 2 2 0 2 |one_bit_adder:U_3_2|:15
- 1 - C 14 OR2 2 2 0 2 |one_bit_adder:U_3_3|:8
- 6 - C 14 OR2 2 2 0 3 |one_bit_adder:U_3_3|:15
- 2 - C 06 OR2 2 2 0 3 |one_bit_adder:U_3_4|:13
- 2 - C 14 OR2 0 3 0 2 |one_bit_adder:U_3_4|:15
- 2 - C 02 OR2 2 2 0 2 |one_bit_adder:U_3_5|:8
- 6 - C 02 OR2 2 2 0 2 |one_bit_adder:U_3_5|:15
- 8 - C 02 OR2 2 2 0 2 |one_bit_adder:U_3_6|:8
- 5 - C 02 OR2 2 2 0 2 |one_bit_adder:U_3_6|:15
- 4 - C 05 OR2 2 2 1 0 |one_bit_adder:U_4_0|:7
- 3 - C 05 OR2 2 2 0 2 |one_bit_adder:U_4_0|:12
- 5 - C 22 OR2 s 2 1 0 2 |one_bit_adder:U_4_1|~8~1
- 7 - C 22 OR2 2 2 0 2 |one_bit_adder:U_4_1|:15
- 8 - C 22 OR2 2 2 0 2 |one_bit_adder:U_4_2|:8
- 1 - C 22 OR2 2 2 0 3 |one_bit_adder:U_4_2|:15
- 7 - C 14 OR2 2 2 0 3 |one_bit_adder:U_4_3|:13
- 3 - C 14 OR2 0 3 0 2 |one_bit_adder:U_4_3|:15
- 6 - C 15 OR2 2 2 0 2 |one_bit_adder:U_4_4|:8
- 7 - C 15 OR2 2 2 0 2 |one_bit_adder:U_4_4|:15
- 1 - C 20 OR2 2 2 0 2 |one_bit_adder:U_4_5|:8
- 3 - C 20 OR2 2 2 0 2 |one_bit_adder:U_4_5|:15
- 4 - C 20 OR2 2 2 0 2 |one_bit_adder:U_4_6|:8
- 7 - C 20 OR2 2 2 0 2 |one_bit_adder:U_4_6|:15
- 3 - C 22 OR2 2 2 1 0 |one_bit_adder:U_5_0|:7
- 6 - C 22 OR2 2 2 0 2 |one_bit_adder:U_5_0|:12
- 2 - C 22 OR2 2 2 1 0 |one_bit_adder:U_5_1|:8
- 4 - C 22 OR2 2 2 0 2 |one_bit_adder:U_5_1|:15
- 4 - C 15 OR2 0 2 1 0 |one_bit_adder:U_5_2|:8
- 5 - C 14 OR2 2 2 0 2 |one_bit_adder:U_5_2|:13
- 5 - C 15 OR2 0 3 0 2 |one_bit_adder:U_5_2|:15
- 1 - C 15 OR2 2 2 1 0 |one_bit_adder:U_5_3|:8
- 8 - C 15 OR2 2 2 0 2 |one_bit_adder:U_5_3|:15
- 2 - C 15 OR2 2 2 1 0 |one_bit_adder:U_5_4|:8
- 3 - C 15 OR2 2 2 0 2 |one_bit_adder:U_5_4|:15
- 8 - C 20 OR2 2 2 1 0 |one_bit_adder:U_5_5|:8
- 5 - C 20 OR2 2 2 0 2 |one_bit_adder:U_5_5|:15
- 2 - C 20 OR2 2 2 1 0 |one_bit_adder:U_5_6|:8
- 6 - C 20 OR2 2 2 1 0 |one_bit_adder:U_5_6|:15
- 1 - C 11 AND2 2 0 1 0 :5144
- 3 - C 11 AND2 2 0 0 4 :5182
- 5 - C 03 AND2 2 0 0 4 :5201
- 6 - C 10 AND2 2 0 0 6 :5239
- 4 - C 10 AND2 2 0 0 5 :5487
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: e:\mydds\verilog\chengfa2.rpt
chengfa2
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 1/ 48( 2%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
B: 1/ 96( 1%) 1/ 48( 2%) 0/ 48( 0%) 1/16( 6%) 1/16( 6%) 0/16( 0%)
C: 27/ 96( 28%) 24/ 48( 50%) 9/ 48( 18%) 6/16( 37%) 3/16( 18%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
12: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
16: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
20: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
21: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
22: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
23: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\mydds\verilog\chengfa2.rpt
chengfa2
** EQUATIONS **
A0 : INPUT;
A1 : INPUT;
A2 : INPUT;
A3 : INPUT;
A4 : INPUT;
A5 : INPUT;
A6 : INPUT;
A7 : INPUT;
B0 : INPUT;
B1 : INPUT;
B2 : INPUT;
B3 : INPUT;
B4 : INPUT;
B5 : INPUT;
B6 : INPUT;
-- Node name is 'B0~1'
-- Equation name is 'B0~1', location is LC6_C3, type is buried.
-- synthesized logic cell
_LC6_C3 = LCELL( _EQ001);
_EQ001 = A2 & B1 & _LC5_C3;
-- Node name is 'B0~2'
-- Equation name is 'B0~2', location is LC8_C3, type is buried.
-- synthesized logic cell
_LC8_C3 = LCELL( _EQ002);
_EQ002 = _LC4_C10 & _LC5_C3;
-- Node name is 'B3~1'
-- Equation name is 'B3~1', location is LC2_C7, type is buried.
-- synthesized logic cell
_LC2_C7 = LCELL( _EQ003);
_EQ003 = A5 & B3 & !_LC3_C7 & _LC4_C7
# A5 & B3 & _LC3_C7 & !_LC4_C7;
-- Node name is 'B4~1'
-- Equation name is 'B4~1', location is LC6_C6, type is buried.
-- synthesized logic cell
_LC6_C6 = LCELL( _EQ004);
_EQ004 = A4 & B4 & !_LC5_C7 & _LC8_C6
# A4 & B4 & _LC5_C7 & !_LC8_C6;
-- Node name is 'B5~1'
-- Equation name is 'B5~1', location is LC8_C14, type is buried.
-- synthesized logic cell
_LC8_C14 = LCELL( _EQ005);
_EQ005 = A3 & B5 & !_LC2_C6 & _LC6_C14
# A3 & B5 & _LC2_C6 & !_LC6_C14;
-- Node name is 'B6~1'
-- Equation name is 'B6~1', location is LC4_C14, type is buried.
-- synthesized logic cell
_LC4_C14 = LCELL( _EQ006);
_EQ006 = A2 & B6 & _LC1_C22 & !_LC7_C14
# A2 & B6 & !_LC1_C22 & _LC7_C14;
-- Node name is 'data_out0'
-- Equation name is 'data_out0', type is output
data_out0 = _LC1_C11;
-- Node name is 'data_out1'
-- Equation name is 'data_out1', type is output
data_out1 = _LC5_C11;
-- Node name is 'data_out2'
-- Equation name is 'data_out2', type is output
data_out2 = _LC6_C11;
-- Node name is 'data_out3'
-- Equation name is 'data_out3', type is output
data_out3 = _LC2_C1;
-- Node name is 'data_out4'
-- Equation name is 'data_out4', type is output
data_out4 = _LC2_C8;
-- Node name is 'data_out5'
-- Equation name is 'data_out5', type is output
data_out5 = _LC4_C5;
-- Node name is 'data_out6'
-- Equation name is 'data_out6', type is output
data_out6 = _LC3_C22;
-- Node name is 'data_out7'
-- Equation name is 'data_out7', type is output
data_out7 = _LC2_C22;
-- Node name is 'data_out8'
-- Equation name is 'data_out8', type is output
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