📄 kbscan.rpt
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Device-Specific Information: e:\zong\verilog\kbscan.rpt
kbscan
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 2 clk_kb
Device-Specific Information: e:\zong\verilog\kbscan.rpt
kbscan
** EQUATIONS **
clk_kb : INPUT;
row0 : INPUT;
row1 : INPUT;
row2 : INPUT;
row3 : INPUT;
-- Node name is ':16' = 'cnt0'
-- Equation name is 'cnt0', location is LC6_A2, type is buried.
cnt0 = DFFE( _EQ001, GLOBAL( clk_kb), VCC, VCC, VCC);
_EQ001 = cnt0 & !_LC4_A2
# !cnt0 & _LC4_A2;
-- Node name is ':15' = 'cnt1'
-- Equation name is 'cnt1', location is LC8_A2, type is buried.
cnt1 = DFFE( _EQ002, GLOBAL( clk_kb), VCC, VCC, VCC);
_EQ002 = !cnt0 & cnt1
# cnt0 & !cnt1 & _LC4_A2
# cnt1 & !_LC4_A2;
-- Node name is 'col0'
-- Equation name is 'col0', type is output
col0 = !_LC8_A1;
-- Node name is 'col1'
-- Equation name is 'col1', type is output
col1 = !_LC1_A1;
-- Node name is 'col2'
-- Equation name is 'col2', type is output
col2 = !_LC3_A1;
-- Node name is 'col3'
-- Equation name is 'col3', type is output
col3 = _LC4_A1;
-- Node name is 'data0'
-- Equation name is 'data0', type is output
data0 = TRI(_LC4_A5, !_LC1_A5);
-- Node name is 'data1'
-- Equation name is 'data1', type is output
data1 = TRI(_LC5_A8, !_LC1_A5);
-- Node name is 'data2'
-- Equation name is 'data2', type is output
data2 = TRI(_LC1_A8, !_LC1_A5);
-- Node name is 'data3'
-- Equation name is 'data3', type is output
data3 = TRI(_LC7_A3, !_LC1_A5);
-- Node name is 'int0'
-- Equation name is 'int0', type is output
int0 = _LC3_A5;
-- Node name is ':30'
-- Equation name is '_LC4_A2', type is buried
_LC4_A2 = LCELL( _EQ003);
_EQ003 = row0 & row1 & row2 & row3;
-- Node name is ':292'
-- Equation name is '_LC5_A2', type is buried
!_LC5_A2 = _LC5_A2~NOT;
_LC5_A2~NOT = LCELL( _EQ004);
_EQ004 = !row1
# !row0
# !row2
# row3;
-- Node name is ':307'
-- Equation name is '_LC3_A2', type is buried
!_LC3_A2 = _LC3_A2~NOT;
_LC3_A2~NOT = LCELL( _EQ005);
_EQ005 = !row1
# !row0
# row2
# !row3;
-- Node name is ':322'
-- Equation name is '_LC7_A2', type is buried
!_LC7_A2 = _LC7_A2~NOT;
_LC7_A2~NOT = LCELL( _EQ006);
_EQ006 = !row3
# !row2
# row1
# !row0;
-- Node name is ':337'
-- Equation name is '_LC2_A2', type is buried
!_LC2_A2 = _LC2_A2~NOT;
_LC2_A2~NOT = LCELL( _EQ007);
_EQ007 = !row3
# !row2
# row0
# !row1;
-- Node name is ':424'
-- Equation name is '_LC6_A5', type is buried
!_LC6_A5 = _LC6_A5~NOT;
_LC6_A5~NOT = LCELL( _EQ008);
_EQ008 = !_LC2_A2 & !_LC3_A2;
-- Node name is ':832'
-- Equation name is '_LC5_A5', type is buried
!_LC5_A5 = _LC5_A5~NOT;
_LC5_A5~NOT = LCELL( _EQ009);
_EQ009 = !_LC5_A2 & !_LC7_A2;
-- Node name is ':1087'
-- Equation name is '_LC3_A8', type is buried
_LC3_A8 = LCELL( _EQ010);
_EQ010 = _LC7_A2
# _LC3_A2;
-- Node name is ':1162'
-- Equation name is '_LC3_A1', type is buried
_LC3_A1 = LCELL( _EQ011);
_EQ011 = !cnt0 & cnt1;
-- Node name is ':1170'
-- Equation name is '_LC1_A1', type is buried
_LC1_A1 = LCELL( _EQ012);
_EQ012 = cnt0 & !cnt1;
-- Node name is ':1178'
-- Equation name is '_LC8_A1', type is buried
_LC8_A1 = LCELL( _EQ013);
_EQ013 = !cnt0 & !cnt1;
-- Node name is ':1181'
-- Equation name is '_LC4_A1', type is buried
_LC4_A1 = LCELL( _EQ014);
_EQ014 = !cnt1
# !cnt0;
-- Node name is '~1229~1'
-- Equation name is '~1229~1', location is LC8_A5, type is buried.
-- synthesized logic cell
_LC8_A5 = LCELL( _EQ015);
_EQ015 = _LC5_A2 & !_LC7_A2
# _LC3_A2 & !_LC7_A2
# !_LC3_A1 & _LC7_A2
# !_LC3_A1 & _LC3_A2
# !_LC3_A1 & _LC5_A2;
-- Node name is ':1235'
-- Equation name is '_LC2_A5', type is buried
_LC2_A5 = LCELL( _EQ016);
_EQ016 = !_LC1_A1 & !_LC2_A2 & _LC8_A5
# _LC1_A1 & _LC1_A2;
-- Node name is '~1236~1'
-- Equation name is '~1236~1', location is LC1_A2, type is buried.
-- synthesized logic cell
_LC1_A2 = LCELL( _EQ017);
_EQ017 = !_LC2_A2 & _LC5_A2 & !_LC7_A2
# !_LC2_A2 & _LC3_A2 & !_LC7_A2;
-- Node name is ':1241'
-- Equation name is '_LC7_A3', type is buried
_LC7_A3 = LCELL( _EQ018);
_EQ018 = _LC2_A5 & !_LC8_A1
# _LC5_A2 & _LC8_A1;
-- Node name is '~1265~1'
-- Equation name is '~1265~1', location is LC7_A8, type is buried.
-- synthesized logic cell
_LC7_A8 = LCELL( _EQ019);
_EQ019 = !_LC3_A1 & _LC3_A8
# _LC3_A1 & _LC7_A2
# _LC5_A2;
-- Node name is '~1265~2'
-- Equation name is '~1265~2', location is LC8_A8, type is buried.
-- synthesized logic cell
_LC8_A8 = LCELL( _EQ020);
_EQ020 = !_LC1_A1 & !_LC2_A2 & _LC7_A8
# _LC1_A1 & _LC7_A2;
-- Node name is ':1265'
-- Equation name is '_LC1_A8', type is buried
_LC1_A8 = LCELL( _EQ021);
_EQ021 = !_LC8_A1 & _LC8_A8
# !_LC2_A2 & _LC3_A8 & _LC8_A1;
-- Node name is '~1289~1'
-- Equation name is '~1289~1', location is LC2_A8, type is buried.
-- synthesized logic cell
_LC2_A8 = LCELL( _EQ022);
_EQ022 = _LC5_A2
# _LC2_A2;
-- Node name is '~1289~2'
-- Equation name is '~1289~2', location is LC4_A8, type is buried.
-- synthesized logic cell
_LC4_A8 = LCELL( _EQ023);
_EQ023 = cnt0 & cnt1 & !_LC2_A8 & _LC3_A8
# !cnt0 & !cnt1 & !_LC2_A8 & _LC3_A8
# cnt0 & !cnt1 & _LC2_A8;
-- Node name is '~1289~3'
-- Equation name is '~1289~3', location is LC6_A8, type is buried.
-- synthesized logic cell
_LC6_A8 = LCELL( _EQ024);
_EQ024 = !_LC1_A1 & _LC3_A1 & _LC7_A2
# _LC2_A2 & _LC3_A1;
-- Node name is ':1289'
-- Equation name is '_LC5_A8', type is buried
_LC5_A8 = LCELL( _EQ025);
_EQ025 = _LC4_A8 & !_LC8_A1
# _LC6_A8 & !_LC8_A1
# _LC1_A2 & _LC8_A1;
-- Node name is ':1310'
-- Equation name is '_LC1_A5', type is buried
!_LC1_A5 = _LC1_A5~NOT;
_LC1_A5~NOT = LCELL( _EQ026);
_EQ026 = _LC5_A5
# _LC6_A5;
-- Node name is '~1313~1'
-- Equation name is '~1313~1', location is LC7_A5, type is buried.
-- synthesized logic cell
!_LC7_A5 = _LC7_A5~NOT;
_LC7_A5~NOT = LCELL( _EQ027);
_EQ027 = !_LC3_A1 & !_LC8_A1
# _LC1_A1 & !_LC8_A1;
-- Node name is ':1313'
-- Equation name is '_LC4_A5', type is buried
_LC4_A5 = LCELL( _EQ028);
_EQ028 = _LC6_A5 & _LC7_A5
# !_LC2_A2 & _LC5_A5 & !_LC7_A5;
-- Node name is ':1325'
-- Equation name is '_LC3_A5', type is buried
_LC3_A5 = LCELL( _EQ029);
_EQ029 = !_LC5_A5 & !_LC6_A5;
Project Information e:\zong\verilog\kbscan.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 16,765K
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