bidir.v

来自「在采用 320x240 屏的设计实验箱上运行」· Verilog 代码 · 共 42 行

module bidir( 
       hwr_, 
       hrd_, 
       hd, 
       swr_, 
       srd_, 
       sd, 
       dumy 
); 

input  hwr_; 
input  hrd_; 
inout  [7:0]    hd; 
output swr_; 
output srd_; 
inout  [7:0]    sd; 
input  dumy; 

wire hd_out_oe; 
reg [7:0]  hd_out; 
wire sd_out_oe; 
reg [7:0]  sd_out; 

always @(hwr_) 
begin 
       if (!hwr_)       sd_out = hd; 
end 

always @(hrd_) 
begin 
       if (!hrd_) hd_out = sd; 
end

assign swr_ = hwr_; 
assign srd_ = hrd_; 
assign sd_out_oe = !hwr_ & dumy; 
//assign sd_out_oe = !hwr_; 
assign hd_out_oe = !hrd_; 
assign hd = hd_out_oe ? hd_out : 8'hzz; 
assign sd = sd_out_oe ? sd_out : 8'hzz; 
endmodule